📄 x225_dif.h
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#define X225_IDE_PIO_CONTROL__PRI_MASTR_POSTWRITE_EN__SHIFT 5#define X225_IDE_PIO_CONTROL__PRI_SLAVE_PREFETCH_EN__SIZE 1#define X225_IDE_PIO_CONTROL__PRI_SLAVE_PREFETCH_EN__MASK 0x00000040#define X225_IDE_PIO_CONTROL__PRI_SLAVE_PREFETCH_EN__SHIFT 6#define X225_IDE_PIO_CONTROL__PRI_MASTR_PREFETCH_EN__SIZE 1#define X225_IDE_PIO_CONTROL__PRI_MASTR_PREFETCH_EN__MASK 0x00000080#define X225_IDE_PIO_CONTROL__PRI_MASTR_PREFETCH_EN__SHIFT 7#define X225_IDE_PIO_CONTROL__SEC_SLAVE_POSTWRITE_EN__SIZE 1#define X225_IDE_PIO_CONTROL__SEC_SLAVE_POSTWRITE_EN__MASK 0x00001000#define X225_IDE_PIO_CONTROL__SEC_SLAVE_POSTWRITE_EN__SHIFT 12#define X225_IDE_PIO_CONTROL__SEC_MASTR_POSTWRITE_EN__SIZE 1#define X225_IDE_PIO_CONTROL__SEC_MASTR_POSTWRITE_EN__MASK 0x00002000#define X225_IDE_PIO_CONTROL__SEC_MASTR_POSTWRITE_EN__SHIFT 13#define X225_IDE_PIO_CONTROL__SEC_SLAVE_PREFETCH_EN__SIZE 1#define X225_IDE_PIO_CONTROL__SEC_SLAVE_PREFETCH_EN__MASK 0x00004000#define X225_IDE_PIO_CONTROL__SEC_SLAVE_PREFETCH_EN__SHIFT 14#define X225_IDE_PIO_CONTROL__SEC_MASTR_PREFETCH_EN__SIZE 1#define X225_IDE_PIO_CONTROL__SEC_MASTR_PREFETCH_EN__MASK 0x00008000#define X225_IDE_PIO_CONTROL__SEC_MASTR_PREFETCH_EN__SHIFT 15/* REGISTER: IDE_PIO_MODE */#define X225_IDE_PIO_MODE__SIZE 16#define X225_IDE_PIO_MODE__BYTELANE 2#define X225_IDE_PIO_MODE__WRMASK 0x00007777#define X225_IDE_PIO_MODE__RDMASK 0x00007777#define X225_IDE_PIO_MODE__WOMASK 0x00000000#define pciideX225_IDE_PIO_MODE 0x0062#define X225_IDE_PIO_MODE__PRI_MASTR_ACCESS_MODE__SIZE 3#define X225_IDE_PIO_MODE__PRI_MASTR_ACCESS_MODE__MASK 0x00000007#define X225_IDE_PIO_MODE__PRI_MASTR_ACCESS_MODE__SHIFT 0#define X225_IDE_PIO_MODE__PRI_SLAVE_ACCESS_MODE__SIZE 3#define X225_IDE_PIO_MODE__PRI_SLAVE_ACCESS_MODE__MASK 0x00000070#define X225_IDE_PIO_MODE__PRI_SLAVE_ACCESS_MODE__SHIFT 4#define X225_IDE_PIO_MODE__SEC_MASTR_ACCESS_MODE__SIZE 3#define X225_IDE_PIO_MODE__SEC_MASTR_ACCESS_MODE__MASK 0x00000700#define X225_IDE_PIO_MODE__SEC_MASTR_ACCESS_MODE__SHIFT 8#define X225_IDE_PIO_MODE__SEC_SLAVE_ACCESS_MODE__SIZE 3#define X225_IDE_PIO_MODE__SEC_SLAVE_ACCESS_MODE__MASK 0x00007000#define X225_IDE_PIO_MODE__SEC_SLAVE_ACCESS_MODE__SHIFT 12/* REGISTER: IDE_DMA_MODE */#define X225_IDE_DMA_MODE__SIZE 32#define X225_IDE_DMA_MODE__BYTELANE 0#define X225_IDE_DMA_MODE__WRMASK 0x17171717#define X225_IDE_DMA_MODE__RDMASK 0x17171717#define X225_IDE_DMA_MODE__WOMASK 0x00000000#define pciideX225_IDE_DMA_MODE 0x0064#define X225_IDE_DMA_MODE__PRI_MASTR_ACCESS_MODE__SIZE 3#define X225_IDE_DMA_MODE__PRI_MASTR_ACCESS_MODE__MASK 0x00000007#define X225_IDE_DMA_MODE__PRI_MASTR_ACCESS_MODE__SHIFT 0#define X225_IDE_DMA_MODE__PRI_MASTR_ULTRA_ENABLE__SIZE 1#define X225_IDE_DMA_MODE__PRI_MASTR_ULTRA_ENABLE__MASK 0x00000010#define X225_IDE_DMA_MODE__PRI_MASTR_ULTRA_ENABLE__SHIFT 4#define X225_IDE_DMA_MODE__PRI_SLAVE_ACCESS_MODE__SIZE 3#define X225_IDE_DMA_MODE__PRI_SLAVE_ACCESS_MODE__MASK 0x00000700#define X225_IDE_DMA_MODE__PRI_SLAVE_ACCESS_MODE__SHIFT 8#define X225_IDE_DMA_MODE__PRI_SLAVE_ULTRA_ENABLE__SIZE 1#define X225_IDE_DMA_MODE__PRI_SLAVE_ULTRA_ENABLE__MASK 0x00001000#define X225_IDE_DMA_MODE__PRI_SLAVE_ULTRA_ENABLE__SHIFT 12#define X225_IDE_DMA_MODE__SEC_MASTR_ACCESS_MODE__SIZE 3#define X225_IDE_DMA_MODE__SEC_MASTR_ACCESS_MODE__MASK 0x00070000#define X225_IDE_DMA_MODE__SEC_MASTR_ACCESS_MODE__SHIFT 16#define X225_IDE_DMA_MODE__SEC_MASTR_ULTRA_ENABLE__SIZE 1#define X225_IDE_DMA_MODE__SEC_MASTR_ULTRA_ENABLE__MASK 0x00100000#define X225_IDE_DMA_MODE__SEC_MASTR_ULTRA_ENABLE__SHIFT 20#define X225_IDE_DMA_MODE__SEC_SLAVE_ACCESS_MODE__SIZE 3#define X225_IDE_DMA_MODE__SEC_SLAVE_ACCESS_MODE__MASK 0x07000000#define X225_IDE_DMA_MODE__SEC_SLAVE_ACCESS_MODE__SHIFT 24#define X225_IDE_DMA_MODE__SEC_SLAVE_ULTRA_ENABLE__SIZE 1#define X225_IDE_DMA_MODE__SEC_SLAVE_ULTRA_ENABLE__MASK 0x10000000#define X225_IDE_DMA_MODE__SEC_SLAVE_ULTRA_ENABLE__SHIFT 28/* REGISTER: IDE_PCI_BUSMASTER_CNTL */#define X225_IDE_PCI_BUSMASTER_CNTL__SIZE 32#define X225_IDE_PCI_BUSMASTER_CNTL__BYTELANE 0#define X225_IDE_PCI_BUSMASTER_CNTL__WRMASK 0x00000e61#define X225_IDE_PCI_BUSMASTER_CNTL__RDMASK 0x00000e60#define X225_IDE_PCI_BUSMASTER_CNTL__WOMASK 0x00000001#define pciideX225_IDE_PCI_BUSMASTER_CNTL 0x0074#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RESET__SIZE 1#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RESET__MASK 0x00000001#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RESET__SHIFT 0#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_READ_COMBINE_EN__SIZE 1#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_READ_COMBINE_EN__MASK 0x00000020#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_READ_COMBINE_EN__SHIFT 5#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_WRT_COMBINE_EN__SIZE 1#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_WRT_COMBINE_EN__MASK 0x00000040#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_WRT_COMBINE_EN__SHIFT 6#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RD_MULT__SIZE 1#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RD_MULT__MASK 0x00000200#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RD_MULT__SHIFT 9#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RD_LINE__SIZE 1#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RD_LINE__MASK 0x00000400#define X225_IDE_PCI_BUSMASTER_CNTL__BUS_MSTR_RD_LINE__SHIFT 10#define X225_IDE_PCI_BUSMASTER_CNTL__LAT_16X__SIZE 1#define X225_IDE_PCI_BUSMASTER_CNTL__LAT_16X__MASK 0x00000800#define X225_IDE_PCI_BUSMASTER_CNTL__LAT_16X__SHIFT 11/* REGISTER: IDE_PCI_BUSSLAVE_CNTL */#define X225_IDE_PCI_BUSSLAVE_CNTL__SIZE 32#define X225_IDE_PCI_BUSSLAVE_CNTL__BYTELANE 0#define X225_IDE_PCI_BUSSLAVE_CNTL__WRMASK 0x00000f1d#define X225_IDE_PCI_BUSSLAVE_CNTL__RDMASK 0x00000f1f#define X225_IDE_PCI_BUSSLAVE_CNTL__WOMASK 0x00000000#define pciideX225_IDE_PCI_BUSSLAVE_CNTL 0x0078#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_IOREAD_SOFTRESET__SIZE 1#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_IOREAD_SOFTRESET__MASK 0x00000001#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_IOREAD_SOFTRESET__SHIFT 0#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_READ_BURST__SIZE 1#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_READ_BURST__MASK 0x00000002#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_READ_BURST__SHIFT 1#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_RDY_READ_DLY__SIZE 1#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_RDY_READ_DLY__MASK 0x00000004#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_RDY_READ_DLY__SHIFT 2#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_PCI_READ_RETRY_EN__SIZE 1#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_PCI_READ_RETRY_EN__MASK 0x00000008#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_PCI_READ_RETRY_EN__SHIFT 3#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_PCI_WRT_RETRY_EN__SIZE 1#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_PCI_WRT_RETRY_EN__MASK 0x00000010#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_PCI_WRT_RETRY_EN__SHIFT 4#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_RETRY_WS__SIZE 4#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_RETRY_WS__MASK 0x00000f00#define X225_IDE_PCI_BUSSLAVE_CNTL__BUS_RETRY_WS__SHIFT 8/* REGISTER: IDE_PRI_BM_STATUS */#define X225_IDE_PRI_BM_STATUS__SIZE 8#define X225_IDE_PRI_BM_STATUS__BYTELANE 2#define X225_IDE_PRI_BM_STATUS__WRMASK 0x00000066#define X225_IDE_PRI_BM_STATUS__RDMASK 0x000000e7#define X225_IDE_PRI_BM_STATUS__WOMASK 0x00000000#define ioideX225_IDE_PRI_BM_STATUS 0x0002#define X225_IDE_PRI_BM_STATUS__BM_IDE_ACTIVE__SIZE 1#define X225_IDE_PRI_BM_STATUS__BM_IDE_ACTIVE__MASK 0x00000001#define X225_IDE_PRI_BM_STATUS__BM_IDE_ACTIVE__SHIFT 0#define X225_IDE_PRI_BM_STATUS__BM_DMA_ERROR__SIZE 1#define X225_IDE_PRI_BM_STATUS__BM_DMA_ERROR__MASK 0x00000002#define X225_IDE_PRI_BM_STATUS__BM_DMA_ERROR__SHIFT 1#define X225_IDE_PRI_BM_STATUS__BM_INTERRUPT__SIZE 1#define X225_IDE_PRI_BM_STATUS__BM_INTERRUPT__MASK 0x00000004#define X225_IDE_PRI_BM_STATUS__BM_INTERRUPT__SHIFT 2#define X225_IDE_PRI_BM_STATUS__DRIVE0_DMA_CAPABLE__SIZE 1#define X225_IDE_PRI_BM_STATUS__DRIVE0_DMA_CAPABLE__MASK 0x00000020#define X225_IDE_PRI_BM_STATUS__DRIVE0_DMA_CAPABLE__SHIFT 5#define X225_IDE_PRI_BM_STATUS__DRIVE1_DMA_CAPABLE__SIZE 1#define X225_IDE_PRI_BM_STATUS__DRIVE1_DMA_CAPABLE__MASK 0x00000040#define X225_IDE_PRI_BM_STATUS__DRIVE1_DMA_CAPABLE__SHIFT 6#define X225_IDE_PRI_BM_STATUS__SIMPLEX_ONLY__SIZE 1#define X225_IDE_PRI_BM_STATUS__SIMPLEX_ONLY__MASK 0x00000080#define X225_IDE_PRI_BM_STATUS__SIMPLEX_ONLY__SHIFT 7/* REGISTER: IDE_SEC_BM_COMMAND */#define X225_IDE_SEC_BM_COMMAND__SIZE 8#define X225_IDE_SEC_BM_COMMAND__BYTELANE 0#define X225_IDE_SEC_BM_COMMAND__WRMASK 0x00000009#define X225_IDE_SEC_BM_COMMAND__RDMASK 0x00000009#define X225_IDE_SEC_BM_COMMAND__WOMASK 0x00000000#define ioideX225_IDE_SEC_BM_COMMAND 0x0008#define X225_IDE_SEC_BM_COMMAND__BM_START_STOP__SIZE 1#define X225_IDE_SEC_BM_COMMAND__BM_START_STOP__MASK 0x00000001#define X225_IDE_SEC_BM_COMMAND__BM_START_STOP__SHIFT 0#define X225_IDE_SEC_BM_COMMAND__BM_DIRECTION__SIZE 1#define X225_IDE_SEC_BM_COMMAND__BM_DIRECTION__MASK 0x00000008#define X225_IDE_SEC_BM_COMMAND__BM_DIRECTION__SHIFT 3/* REGISTER: IDE_SEC_BM_STATUS */#define X225_IDE_SEC_BM_STATUS__SIZE 8#define X225_IDE_SEC_BM_STATUS__BYTELANE 2#define X225_IDE_SEC_BM_STATUS__WRMASK 0x00000066#define X225_IDE_SEC_BM_STATUS__RDMASK 0x000000e7#define X225_IDE_SEC_BM_STATUS__WOMASK 0x00000000#define ioideX225_IDE_SEC_BM_STATUS 0x000A#define X225_IDE_SEC_BM_STATUS__BM_IDE_ACTIVE__SIZE 1#define X225_IDE_SEC_BM_STATUS__BM_IDE_ACTIVE__MASK 0x00000001#define X225_IDE_SEC_BM_STATUS__BM_IDE_ACTIVE__SHIFT 0#define X225_IDE_SEC_BM_STATUS__BM_DMA_ERROR__SIZE 1#define X225_IDE_SEC_BM_STATUS__BM_DMA_ERROR__MASK 0x00000002#define X225_IDE_SEC_BM_STATUS__BM_DMA_ERROR__SHIFT 1#define X225_IDE_SEC_BM_STATUS__BM_INTERRUPT__SIZE 1#define X225_IDE_SEC_BM_STATUS__BM_INTERRUPT__MASK 0x00000004#define X225_IDE_SEC_BM_STATUS__BM_INTERRUPT__SHIFT 2#define X225_IDE_SEC_BM_STATUS__DRIVE0_DMA_CAPABLE__SIZE 1#define X225_IDE_SEC_BM_STATUS__DRIVE0_DMA_CAPABLE__MASK 0x00000020#define X225_IDE_SEC_BM_STATUS__DRIVE0_DMA_CAPABLE__SHIFT 5#define X225_IDE_SEC_BM_STATUS__DRIVE1_DMA_CAPABLE__SIZE 1#define X225_IDE_SEC_BM_STATUS__DRIVE1_DMA_CAPABLE__MASK 0x00000040#define X225_IDE_SEC_BM_STATUS__DRIVE1_DMA_CAPABLE__SHIFT 6#define X225_IDE_SEC_BM_STATUS__SIMPLEX_ONLY__SIZE 1#define X225_IDE_SEC_BM_STATUS__SIMPLEX_ONLY__MASK 0x00000080#define X225_IDE_SEC_BM_STATUS__SIMPLEX_ONLY__SHIFT 7⌨️ 快捷键说明
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