x225_dif.h

for mips adm5120 uclibc-0.9.19 toolchain

#define X225_IDE_STATUS__DEVSEL_TIMING__MASK                              0x00000600
#define X225_IDE_STATUS__DEVSEL_TIMING__SHIFT                             9
#define X225_IDE_STATUS__SIGNALED_TARGET_ABORT__SIZE                      1
#define X225_IDE_STATUS__SIGNALED_TARGET_ABORT__MASK                      0x00000800
#define X225_IDE_STATUS__SIGNALED_TARGET_ABORT__SHIFT                     11
#define X225_IDE_STATUS__RECEIVED_TARGET_ABORT__SIZE                      1
#define X225_IDE_STATUS__RECEIVED_TARGET_ABORT__MASK                      0x00001000
#define X225_IDE_STATUS__RECEIVED_TARGET_ABORT__SHIFT                     12
#define X225_IDE_STATUS__RECEIVED_MASTER_ABORT__SIZE                      1
#define X225_IDE_STATUS__RECEIVED_MASTER_ABORT__MASK                      0x00002000
#define X225_IDE_STATUS__RECEIVED_MASTER_ABORT__SHIFT                     13
#define X225_IDE_STATUS__SIGNALED_SYSTEM_ERROR__SIZE                      1
#define X225_IDE_STATUS__SIGNALED_SYSTEM_ERROR__MASK                      0x00004000
#define X225_IDE_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                     14
#define X225_IDE_STATUS__PARITY_ERROR_DETECTED__SIZE                      1
#define X225_IDE_STATUS__PARITY_ERROR_DETECTED__MASK                      0x00008000
#define X225_IDE_STATUS__PARITY_ERROR_DETECTED__SHIFT                     15

/* REGISTER:  IDE_PRI0_BASE */

#define X225_IDE_PRI0_BASE__SIZE                                          32
#define X225_IDE_PRI0_BASE__BYTELANE                                      0
#define X225_IDE_PRI0_BASE__WRMASK                                        0xfffffff8
#define X225_IDE_PRI0_BASE__RDMASK                                        0xfffffff9
#define X225_IDE_PRI0_BASE__WOMASK                                        0x00000000

#define pciideX225_IDE_PRI0_BASE                                          0x0010

#define X225_IDE_PRI0_BASE__IO_SPACE__SIZE                                1
#define X225_IDE_PRI0_BASE__IO_SPACE__MASK                                0x00000001
#define X225_IDE_PRI0_BASE__IO_SPACE__SHIFT                               0
#define X225_IDE_PRI0_BASE__IO_BASE_ADDRESS__SIZE                         29
#define X225_IDE_PRI0_BASE__IO_BASE_ADDRESS__MASK                         0xfffffff8
#define X225_IDE_PRI0_BASE__IO_BASE_ADDRESS__SHIFT                        3

/* REGISTER:  IDE_PRI1_BASE */

#define X225_IDE_PRI1_BASE__SIZE                                          32
#define X225_IDE_PRI1_BASE__BYTELANE                                      0
#define X225_IDE_PRI1_BASE__WRMASK                                        0xfffffffc
#define X225_IDE_PRI1_BASE__RDMASK                                        0xfffffffd
#define X225_IDE_PRI1_BASE__WOMASK                                        0x00000000

#define pciideX225_IDE_PRI1_BASE                                          0x0014

#define X225_IDE_PRI1_BASE__IO_SPACE__SIZE                                1
#define X225_IDE_PRI1_BASE__IO_SPACE__MASK                                0x00000001
#define X225_IDE_PRI1_BASE__IO_SPACE__SHIFT                               0
#define X225_IDE_PRI1_BASE__IO_BASE_ADDRESS__SIZE                         30
#define X225_IDE_PRI1_BASE__IO_BASE_ADDRESS__MASK                         0xfffffffc
#define X225_IDE_PRI1_BASE__IO_BASE_ADDRESS__SHIFT                        2

/* REGISTER:  IDE_SEC0_BASE */

#define X225_IDE_SEC0_BASE__SIZE                                          32
#define X225_IDE_SEC0_BASE__BYTELANE                                      0
#define X225_IDE_SEC0_BASE__WRMASK                                        0xfffffff8
#define X225_IDE_SEC0_BASE__RDMASK                                        0xfffffff9
#define X225_IDE_SEC0_BASE__WOMASK                                        0x00000000

#define pciideX225_IDE_SEC0_BASE                                          0x0018

#define X225_IDE_SEC0_BASE__IO_SPACE__SIZE                                1
#define X225_IDE_SEC0_BASE__IO_SPACE__MASK                                0x00000001
#define X225_IDE_SEC0_BASE__IO_SPACE__SHIFT                               0
#define X225_IDE_SEC0_BASE__IO_BASE_ADDRESS__SIZE                         29
#define X225_IDE_SEC0_BASE__IO_BASE_ADDRESS__MASK                         0xfffffff8
#define X225_IDE_SEC0_BASE__IO_BASE_ADDRESS__SHIFT                        3

/* REGISTER:  IDE_SEC1_BASE */

#define X225_IDE_SEC1_BASE__SIZE                                          32
#define X225_IDE_SEC1_BASE__BYTELANE                                      0
#define X225_IDE_SEC1_BASE__WRMASK                                        0xfffffffc
#define X225_IDE_SEC1_BASE__RDMASK                                        0xfffffffd
#define X225_IDE_SEC1_BASE__WOMASK                                        0x00000000

#define pciideX225_IDE_SEC1_BASE                                          0x001C

#define X225_IDE_SEC1_BASE__IO_SPACE__SIZE                                1
#define X225_IDE_SEC1_BASE__IO_SPACE__MASK                                0x00000001
#define X225_IDE_SEC1_BASE__IO_SPACE__SHIFT                               0
#define X225_IDE_SEC1_BASE__IO_BASE_ADDRESS__SIZE                         30
#define X225_IDE_SEC1_BASE__IO_BASE_ADDRESS__MASK                         0xfffffffc
#define X225_IDE_SEC1_BASE__IO_BASE_ADDRESS__SHIFT                        2

/* REGISTER:  IDE_BM_BASE */

#define X225_IDE_BM_BASE__SIZE                                            32
#define X225_IDE_BM_BASE__BYTELANE                                        0
#define X225_IDE_BM_BASE__WRMASK                                          0xfffffff0
#define X225_IDE_BM_BASE__RDMASK                                          0xfffffff1
#define X225_IDE_BM_BASE__WOMASK                                          0x00000000

#define pciideX225_IDE_BM_BASE                                            0x0020

#define X225_IDE_BM_BASE__IO_SPACE__SIZE                                  1
#define X225_IDE_BM_BASE__IO_SPACE__MASK                                  0x00000001
#define X225_IDE_BM_BASE__IO_SPACE__SHIFT                                 0
#define X225_IDE_BM_BASE__IO_BASE_ADDRESS__SIZE                           28
#define X225_IDE_BM_BASE__IO_BASE_ADDRESS__MASK                           0xfffffff0
#define X225_IDE_BM_BASE__IO_BASE_ADDRESS__SHIFT                          4

/* REGISTER:  IDE_TMG_CNTL */

#define X225_IDE_TMG_CNTL__SIZE                                           32
#define X225_IDE_TMG_CNTL__BYTELANE                                       0
#define X225_IDE_TMG_CNTL__WRMASK                                         0x7f7f7f7f
#define X225_IDE_TMG_CNTL__RDMASK                                         0x7f7f7f7f
#define X225_IDE_TMG_CNTL__WOMASK                                         0x00000000

#define pciideX225_IDE_TMG_CNTL                                           0x0040

#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_REG_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_REG_TMG__MASK               0x00000001
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_REG_TMG__SHIFT              0
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_REG_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_REG_AUXTMG__MASK            0x00000002
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_REG_AUXTMG__SHIFT           1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_PIO_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_PIO_TMG__MASK               0x00000004
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_PIO_TMG__SHIFT              2
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_PIO_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_PIO_AUXTMG__MASK            0x00000008
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_PIO_AUXTMG__SHIFT           3
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_MDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_MDMA_TMG__MASK              0x00000010
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_MDMA_TMG__SHIFT             4
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_MDMA_AUXTMG__SIZE           1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_MDMA_AUXTMG__MASK           0x00000020
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_MDMA_AUXTMG__SHIFT          5
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_UDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_UDMA_TMG__MASK              0x00000040
#define X225_IDE_TMG_CNTL__PRI_SLAVE_AUTOCALC_UDMA_TMG__SHIFT             6
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_REG_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_REG_TMG__MASK               0x00000100
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_REG_TMG__SHIFT              8
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_REG_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_REG_AUXTMG__MASK            0x00000200
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_REG_AUXTMG__SHIFT           9
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_PIO_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_PIO_TMG__MASK               0x00000400
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_PIO_TMG__SHIFT              10
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_PIO_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_PIO_AUXTMG__MASK            0x00000800
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_PIO_AUXTMG__SHIFT           11
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_MDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_MDMA_TMG__MASK              0x00001000
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_MDMA_TMG__SHIFT             12
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_MDMA_AUXTMG__SIZE           1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_MDMA_AUXTMG__MASK           0x00002000
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_MDMA_AUXTMG__SHIFT          13
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_UDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_UDMA_TMG__MASK              0x00004000
#define X225_IDE_TMG_CNTL__PRI_MASTR_AUTOCALC_UDMA_TMG__SHIFT             14
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_REG_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_REG_TMG__MASK               0x00010000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_REG_TMG__SHIFT              16
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_REG_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_REG_AUXTMG__MASK            0x00020000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_REG_AUXTMG__SHIFT           17
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_PIO_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_PIO_TMG__MASK               0x00040000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_PIO_TMG__SHIFT              18
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_PIO_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_PIO_AUXTMG__MASK            0x00080000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_PIO_AUXTMG__SHIFT           19
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_MDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_MDMA_TMG__MASK              0x00100000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_MDMA_TMG__SHIFT             20
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_MDMA_AUXTMG__SIZE           1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_MDMA_AUXTMG__MASK           0x00200000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_MDMA_AUXTMG__SHIFT          21
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_UDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_UDMA_TMG__MASK              0x00400000
#define X225_IDE_TMG_CNTL__SEC_SLAVE_AUTOCALC_UDMA_TMG__SHIFT             22
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_REG_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_REG_TMG__MASK               0x01000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_REG_TMG__SHIFT              24
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_REG_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_REG_AUXTMG__MASK            0x02000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_REG_AUXTMG__SHIFT           25
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_PIO_TMG__SIZE               1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_PIO_TMG__MASK               0x04000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_PIO_TMG__SHIFT              26
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_PIO_AUXTMG__SIZE            1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_PIO_AUXTMG__MASK            0x08000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_PIO_AUXTMG__SHIFT           27
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_MDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_MDMA_TMG__MASK              0x10000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_MDMA_TMG__SHIFT             28
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_MDMA_AUXTMG__SIZE           1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_MDMA_AUXTMG__MASK           0x20000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_MDMA_AUXTMG__SHIFT          29
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_UDMA_TMG__SIZE              1
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_UDMA_TMG__MASK              0x40000000
#define X225_IDE_TMG_CNTL__SEC_MASTR_AUTOCALC_UDMA_TMG__SHIFT             30

/* REGISTER:  IDE_PIO_CONTROL */

#define X225_IDE_PIO_CONTROL__SIZE                                        16
#define X225_IDE_PIO_CONTROL__BYTELANE                                    0
#define X225_IDE_PIO_CONTROL__WRMASK                                      0x0000f0f0
#define X225_IDE_PIO_CONTROL__RDMASK                                      0x0000f0f0
#define X225_IDE_PIO_CONTROL__WOMASK                                      0x00000000

#define pciideX225_IDE_PIO_CONTROL                                        0x0060

#define X225_IDE_PIO_CONTROL__PRI_SLAVE_POSTWRITE_EN__SIZE                1
#define X225_IDE_PIO_CONTROL__PRI_SLAVE_POSTWRITE_EN__MASK                0x00000010
#define X225_IDE_PIO_CONTROL__PRI_SLAVE_POSTWRITE_EN__SHIFT               4
#define X225_IDE_PIO_CONTROL__PRI_MASTR_POSTWRITE_EN__SIZE                1
#define X225_IDE_PIO_CONTROL__PRI_MASTR_POSTWRITE_EN__MASK                0x00000020