x225_dif.h

for mips adm5120 uclibc-0.9.19 toolchain

#define X225_TIMER_INTRR_STATS_REG__SIZE                                  32
#define X225_TIMER_INTRR_STATS_REG__BYTELANE                              0
#define X225_TIMER_INTRR_STATS_REG__WRMASK                                0x00000000
#define X225_TIMER_INTRR_STATS_REG__RDMASK                                0x0000003f
#define X225_TIMER_INTRR_STATS_REG__WOMASK                                0x00000000

#define mmX225_TIMER_INTRR_STATS_REG                                      0x2920

#define X225_TIMER_INTRR_STATS_REG__TIMER0_INTRR_REG__SIZE                1
#define X225_TIMER_INTRR_STATS_REG__TIMER0_INTRR_REG__MASK                0x00000001
#define X225_TIMER_INTRR_STATS_REG__TIMER0_INTRR_REG__SHIFT               0
#define X225_TIMER_INTRR_STATS_REG__TIMER1_INTRR_REG__SIZE                1
#define X225_TIMER_INTRR_STATS_REG__TIMER1_INTRR_REG__MASK                0x00000002
#define X225_TIMER_INTRR_STATS_REG__TIMER1_INTRR_REG__SHIFT               1
#define X225_TIMER_INTRR_STATS_REG__TIMER2_INTRR_REG__SIZE                1
#define X225_TIMER_INTRR_STATS_REG__TIMER2_INTRR_REG__MASK                0x00000004
#define X225_TIMER_INTRR_STATS_REG__TIMER2_INTRR_REG__SHIFT               2
#define X225_TIMER_INTRR_STATS_REG__TIMER3_INTRR_REG__SIZE                1
#define X225_TIMER_INTRR_STATS_REG__TIMER3_INTRR_REG__MASK                0x00000008
#define X225_TIMER_INTRR_STATS_REG__TIMER3_INTRR_REG__SHIFT               3
#define X225_TIMER_INTRR_STATS_REG__TIMER4_INTRR_REG__SIZE                1
#define X225_TIMER_INTRR_STATS_REG__TIMER4_INTRR_REG__MASK                0x00000010
#define X225_TIMER_INTRR_STATS_REG__TIMER4_INTRR_REG__SHIFT               4
#define X225_TIMER_INTRR_STATS_REG__TIMER5_INTRR_REG__SIZE                1
#define X225_TIMER_INTRR_STATS_REG__TIMER5_INTRR_REG__MASK                0x00000020
#define X225_TIMER_INTRR_STATS_REG__TIMER5_INTRR_REG__SHIFT               5

/* REGISTER:  TIMER5_INITIALIZE_REG */

#define X225_TIMER5_INITIALIZE_REG__SIZE                                  32
#define X225_TIMER5_INITIALIZE_REG__BYTELANE                              0
#define X225_TIMER5_INITIALIZE_REG__WRMASK                                0xffffffff
#define X225_TIMER5_INITIALIZE_REG__RDMASK                                0xffffffff
#define X225_TIMER5_INITIALIZE_REG__WOMASK                                0x00000000

#define mmX225_TIMER5_INITIALIZE_REG                                      0x2954

#define X225_TIMER5_INITIALIZE_REG__TIMER5_INPUT__SIZE                    32
#define X225_TIMER5_INITIALIZE_REG__TIMER5_INPUT__MASK                    0xffffffff
#define X225_TIMER5_INITIALIZE_REG__TIMER5_INPUT__SHIFT                   0

/* REGISTER:  TIMER5_READBACK_REG */

#define X225_TIMER5_READBACK_REG__SIZE                                    32
#define X225_TIMER5_READBACK_REG__BYTELANE                                0
#define X225_TIMER5_READBACK_REG__WRMASK                                  0x00000000
#define X225_TIMER5_READBACK_REG__RDMASK                                  0xffffffff
#define X225_TIMER5_READBACK_REG__WOMASK                                  0x00000000

#define mmX225_TIMER5_READBACK_REG                                        0x2974

#define X225_TIMER5_READBACK_REG__TIMER5_COUNT__SIZE                      32
#define X225_TIMER5_READBACK_REG__TIMER5_COUNT__MASK                      0xffffffff
#define X225_TIMER5_READBACK_REG__TIMER5_COUNT__SHIFT                     0

/* REGISTER:  RTC_CONT_REG1 */

#define X225_RTC_CONT_REG1__SIZE                                          32
#define X225_RTC_CONT_REG1__BYTELANE                                      0
#define X225_RTC_CONT_REG1__WRMASK                                        0x000001ff
#define X225_RTC_CONT_REG1__RDMASK                                        0x000001ff
#define X225_RTC_CONT_REG1__WOMASK                                        0x00000000

#define mmX225_RTC_CONT_REG1                                              0x2984

#define X225_RTC_CONT_REG1__RTC_RUN_ENABLE__SIZE                          1
#define X225_RTC_CONT_REG1__RTC_RUN_ENABLE__MASK                          0x00000001
#define X225_RTC_CONT_REG1__RTC_RUN_ENABLE__SHIFT                         0
#define X225_RTC_CONT_REG1__LEAP_YEAR__SIZE                               1
#define X225_RTC_CONT_REG1__LEAP_YEAR__MASK                               0x00000002
#define X225_RTC_CONT_REG1__LEAP_YEAR__SHIFT                              1
#define X225_RTC_CONT_REG1__RTC_EVENT0_INTRR_EN__SIZE                     1
#define X225_RTC_CONT_REG1__RTC_EVENT0_INTRR_EN__MASK                     0x00000004
#define X225_RTC_CONT_REG1__RTC_EVENT0_INTRR_EN__SHIFT                    2
#define X225_RTC_CONT_REG1__RTC_EVENT1_INTRR_EN__SIZE                     1
#define X225_RTC_CONT_REG1__RTC_EVENT1_INTRR_EN__MASK                     0x00000008
#define X225_RTC_CONT_REG1__RTC_EVENT1_INTRR_EN__SHIFT                    3
#define X225_RTC_CONT_REG1__RTC_EVENT2_INTRR_EN__SIZE                     1
#define X225_RTC_CONT_REG1__RTC_EVENT2_INTRR_EN__MASK                     0x00000010
#define X225_RTC_CONT_REG1__RTC_EVENT2_INTRR_EN__SHIFT                    4
#define X225_RTC_CONT_REG1__RTC_EVENT3_INTRR_EN__SIZE                     1
#define X225_RTC_CONT_REG1__RTC_EVENT3_INTRR_EN__MASK                     0x00000020
#define X225_RTC_CONT_REG1__RTC_EVENT3_INTRR_EN__SHIFT                    5
#define X225_RTC_CONT_REG1__RTC_EVENT4_INTRR_EN__SIZE                     1
#define X225_RTC_CONT_REG1__RTC_EVENT4_INTRR_EN__MASK                     0x00000040
#define X225_RTC_CONT_REG1__RTC_EVENT4_INTRR_EN__SHIFT                    6
#define X225_RTC_CONT_REG1__RTC_EVENT5_INTRR_EN__SIZE                     1
#define X225_RTC_CONT_REG1__RTC_EVENT5_INTRR_EN__MASK                     0x00000080
#define X225_RTC_CONT_REG1__RTC_EVENT5_INTRR_EN__SHIFT                    7
#define X225_RTC_CONT_REG1__RTC_TEST_MODE__SIZE                           1
#define X225_RTC_CONT_REG1__RTC_TEST_MODE__MASK                           0x00000100
#define X225_RTC_CONT_REG1__RTC_TEST_MODE__SHIFT                          8

/* REGISTER:  RTC_READBACK_REG */

#define X225_RTC_READBACK_REG__SIZE                                       32
#define X225_RTC_READBACK_REG__BYTELANE                                   0
#define X225_RTC_READBACK_REG__WRMASK                                     0x00000000
#define X225_RTC_READBACK_REG__RDMASK                                     0xffffffff
#define X225_RTC_READBACK_REG__WOMASK                                     0x00000000

#define mmX225_RTC_READBACK_REG                                           0x29C4

#define X225_RTC_READBACK_REG__CURRENT_SECONDS__SIZE                      6
#define X225_RTC_READBACK_REG__CURRENT_SECONDS__MASK                      0x0000003f
#define X225_RTC_READBACK_REG__CURRENT_SECONDS__SHIFT                     0
#define X225_RTC_READBACK_REG__CURRENT_MINUTES__SIZE                      6
#define X225_RTC_READBACK_REG__CURRENT_MINUTES__MASK                      0x00000fc0
#define X225_RTC_READBACK_REG__CURRENT_MINUTES__SHIFT                     6
#define X225_RTC_READBACK_REG__CURRENT_HOURS__SIZE                        5
#define X225_RTC_READBACK_REG__CURRENT_HOURS__MASK                        0x0001f000
#define X225_RTC_READBACK_REG__CURRENT_HOURS__SHIFT                       12
#define X225_RTC_READBACK_REG__CURRENT_DAYS__SIZE                         5
#define X225_RTC_READBACK_REG__CURRENT_DAYS__MASK                         0x003e0000
#define X225_RTC_READBACK_REG__CURRENT_DAYS__SHIFT                        17
#define X225_RTC_READBACK_REG__CURRENT_MONTHS__SIZE                       4
#define X225_RTC_READBACK_REG__CURRENT_MONTHS__MASK                       0x03c00000
#define X225_RTC_READBACK_REG__CURRENT_MONTHS__SHIFT                      22
#define X225_RTC_READBACK_REG__YEARS__SIZE                                6
#define X225_RTC_READBACK_REG__YEARS__MASK                                0xfc000000
#define X225_RTC_READBACK_REG__YEARS__SHIFT                               26


/* REGISTER:  SB_REVISION_ID */

#define X225_SB_REVISION_ID__SIZE                                         32
#define X225_SB_REVISION_ID__BYTELANE                                     0
#define X225_SB_REVISION_ID__WRMASK                                       0x00000000
#define X225_SB_REVISION_ID__RDMASK                                       0xffffffff
#define X225_SB_REVISION_ID__WOMASK                                       0x00000000

#define mmX225_SB_REVISION_ID                                             0x0F20

#define X225_SB_REVISION_ID__IDE_REV_ID__SIZE                             8
#define X225_SB_REVISION_ID__IDE_REV_ID__MASK                             0x000000ff
#define X225_SB_REVISION_ID__IDE_REV_ID__SHIFT                            0
#define X225_SB_REVISION_ID__USB_REV_ID__SIZE                             8
#define X225_SB_REVISION_ID__USB_REV_ID__MASK                             0x0000ff00
#define X225_SB_REVISION_ID__USB_REV_ID__SHIFT                            8
#define X225_SB_REVISION_ID__DAIO_REV_ID0__SIZE                           8
#define X225_SB_REVISION_ID__DAIO_REV_ID0__MASK                           0x00ff0000
#define X225_SB_REVISION_ID__DAIO_REV_ID0__SHIFT                          16
#define X225_SB_REVISION_ID__DAIO_REV_ID1__SIZE                           8
#define X225_SB_REVISION_ID__DAIO_REV_ID1__MASK                           0xff000000
#define X225_SB_REVISION_ID__DAIO_REV_ID1__SHIFT                          24

/* REGISTER:  IDE_COMMAND */

#define X225_IDE_COMMAND__SIZE                                            16
#define X225_IDE_COMMAND__BYTELANE                                        0
#define X225_IDE_COMMAND__WRMASK                                          0x00000555
#define X225_IDE_COMMAND__RDMASK                                          0x0000077f
#define X225_IDE_COMMAND__WOMASK                                          0x00000000

#define pciideX225_IDE_COMMAND                                            0x0004

#define X225_IDE_COMMAND__IO_ACCESS_EN__SIZE                              1
#define X225_IDE_COMMAND__IO_ACCESS_EN__MASK                              0x00000001
#define X225_IDE_COMMAND__IO_ACCESS_EN__SHIFT                             0
#define X225_IDE_COMMAND__MEM_ACCESS_EN__SIZE                             1
#define X225_IDE_COMMAND__MEM_ACCESS_EN__MASK                             0x00000002
#define X225_IDE_COMMAND__MEM_ACCESS_EN__SHIFT                            1
#define X225_IDE_COMMAND__BUS_MASTER_EN_CFG__SIZE                         1
#define X225_IDE_COMMAND__BUS_MASTER_EN_CFG__MASK                         0x00000004
#define X225_IDE_COMMAND__BUS_MASTER_EN_CFG__SHIFT                        2
#define X225_IDE_COMMAND__SPECIAL_CYCLE_EN__SIZE                          1
#define X225_IDE_COMMAND__SPECIAL_CYCLE_EN__MASK                          0x00000008
#define X225_IDE_COMMAND__SPECIAL_CYCLE_EN__SHIFT                         3
#define X225_IDE_COMMAND__MEM_WRITE_INVALIDATE_EN__SIZE                   1
#define X225_IDE_COMMAND__MEM_WRITE_INVALIDATE_EN__MASK                   0x00000010
#define X225_IDE_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                  4
#define X225_IDE_COMMAND__PAL_SNOOP_EN__SIZE                              1
#define X225_IDE_COMMAND__PAL_SNOOP_EN__MASK                              0x00000020
#define X225_IDE_COMMAND__PAL_SNOOP_EN__SHIFT                             5
#define X225_IDE_COMMAND__PARITY_ERROR_EN__SIZE                           1
#define X225_IDE_COMMAND__PARITY_ERROR_EN__MASK                           0x00000040
#define X225_IDE_COMMAND__PARITY_ERROR_EN__SHIFT                          6
#define X225_IDE_COMMAND__SERR_EN__SIZE                                   1
#define X225_IDE_COMMAND__SERR_EN__MASK                                   0x00000100
#define X225_IDE_COMMAND__SERR_EN__SHIFT                                  8
#define X225_IDE_COMMAND__FAST_BACK_EN__SIZE                              1
#define X225_IDE_COMMAND__FAST_BACK_EN__MASK                              0x00000200
#define X225_IDE_COMMAND__FAST_BACK_EN__SHIFT                             9
#define X225_IDE_COMMAND__INTERRUPT_DISABLE__SIZE                         1
#define X225_IDE_COMMAND__INTERRUPT_DISABLE__MASK                         0x00000400
#define X225_IDE_COMMAND__INTERRUPT_DISABLE__SHIFT                        10

/* REGISTER:  IDE_STATUS */

#define X225_IDE_STATUS__SIZE                                             16
#define X225_IDE_STATUS__BYTELANE                                         2
#define X225_IDE_STATUS__WRMASK                                           0x0000f100
#define X225_IDE_STATUS__RDMASK                                           0x0000ffb8
#define X225_IDE_STATUS__WOMASK                                           0x00000000

#define pciideX225_IDE_STATUS                                             0x0006

#define X225_IDE_STATUS__INTERRUPT_STATUS__SIZE                           1
#define X225_IDE_STATUS__INTERRUPT_STATUS__MASK                           0x00000008
#define X225_IDE_STATUS__INTERRUPT_STATUS__SHIFT                          3
#define X225_IDE_STATUS__CAP_LIST__SIZE                                   1
#define X225_IDE_STATUS__CAP_LIST__MASK                                   0x00000010
#define X225_IDE_STATUS__CAP_LIST__SHIFT                                  4
#define X225_IDE_STATUS__PCI_66MHZ_CAPABLE__SIZE                          1
#define X225_IDE_STATUS__PCI_66MHZ_CAPABLE__MASK                          0x00000020
#define X225_IDE_STATUS__PCI_66MHZ_CAPABLE__SHIFT                         5
#define X225_IDE_STATUS__FAST_BACK_CAPABLE__SIZE                          1
#define X225_IDE_STATUS__FAST_BACK_CAPABLE__MASK                          0x00000080
#define X225_IDE_STATUS__FAST_BACK_CAPABLE__SHIFT                         7
#define X225_IDE_STATUS__MASTER_DATA_PARITY_ERR__SIZE                     1
#define X225_IDE_STATUS__MASTER_DATA_PARITY_ERR__MASK                     0x00000100
#define X225_IDE_STATUS__MASTER_DATA_PARITY_ERR__SHIFT                    8
#define X225_IDE_STATUS__DEVSEL_TIMING__SIZE                              2