eth.h

来自「for mips adm5120 uclibc-0.9.19 toolchain」· C头文件 代码 · 共 336 行

#ifndef	__IDT_ETH_H__
#define	__IDT_ETH_H__

/*******************************************************************************
 *
 * Copyright 2002 Integrated Device Technology, Inc.
 *		All rights reserved.
 *
 * Ethernet register definition.
 *
 * File   : $Id: eth.h,v 1.1 2004/10/15 12:47:26 brianc Exp $
 *
 * Author : [e-mail]
 * Date   : 20020605
 * Update :
 *	    $Log: eth.h,v $
 *	    Revision 1.1  2004/10/15 12:47:26  brianc
 *	    Readd the file
 *	
 *	    Revision 1.1.1.1  2004/03/29 00:54:44  daniell
 *	    Initialized the project
 *	
 *	    Revision 1.2  2003/07/30 18:20:38  stevel
 *	    MR: 1-2IQL9
 *	
 *	    Add IDT and ATI Xilleon LSP's, and update related drivers.
 *	
 *	    Revision 1.1.2.1  2003/02/15 00:06:01  stevel
 *	    New IDT board support: 79EB438 and 79RP355. Also support for
 *	    boot from PROM on 79S334A, 79EB355, 79RP355, and 79EB438.
 *	
 *	    Revision 1.3  2002/06/06 18:34:04  astichte
 *	    Added XXX_PhysicalAddress and XXX_VirtualAddress
 *	
 *	    Revision 1.2  2002/06/05 18:19:46  astichte
 *	    Added
 *	
 *	    Revision 1.1  2002/05/29 17:33:22  sysarch
 *	    jba File moved from vcode/include/idt/acacia
 *
 ******************************************************************************/

enum
{
	ETH0_PhysicalAddress	= 0x18058000,
	ETH_PhysicalAddress	= ETH0_PhysicalAddress,		// Default

	ETH0_VirtualAddress	= 0xb8058000,
	ETH_VirtualAddress	= ETH0_VirtualAddress,		// Default
	ETH1_PhysicalAddress	= 0x18060000,
	ETH1_VirtualAddress	= 0xb8060000,			// Default
} ;

typedef struct
{
	unsigned int ethintfc		;
	unsigned int ethfifott		;
	unsigned int etharc		;
	unsigned int ethhash0		;
	unsigned int ethhash1		;
	unsigned int ethu0 [4]		;	// Reserved.	
	unsigned int ethpfs		;
	unsigned int ethmcp		;
	unsigned int eth_u1 [10]		;	// Reserved.
	unsigned int ethspare		;
	unsigned int eth_u2 [42]		;	// Reserved. 
	unsigned int ethsal0		;
	unsigned int ethsah0		;
	unsigned int ethsal1		;
	unsigned int ethsah1		;
	unsigned int ethsal2		;
	unsigned int ethsah2		;
	unsigned int ethsal3		;
	unsigned int ethsah3		;
	unsigned int ethrbc		;
	unsigned int ethrpc		;
	unsigned int ethrupc		;
	unsigned int ethrfc		;
	unsigned int ethtbc		;
	unsigned int ethgpf		;
	unsigned int eth_u9 [50]		;	// Reserved.	
	unsigned int ethmac1		;
	unsigned int ethmac2		;
	unsigned int ethipgt		;
	unsigned int ethipgr		;
	unsigned int ethclrt		;
	unsigned int ethmaxf		;
	unsigned int eth_u10		;	// Reserved.	
	unsigned int ethmtest		;
	unsigned int miimcfg		;
	unsigned int miimcmd		;
	unsigned int miimaddr		;
	unsigned int miimwtd		;
	unsigned int miimrdd		;
	unsigned int miimind		;
	unsigned int eth_u11		;	// Reserved.
	unsigned int eth_u12		;	// Reserved.
	unsigned int ethcfsa0		;
	unsigned int ethcfsa1		;
	unsigned int ethcfsa2		;
} volatile *ETH_t;

enum
{
	ETHINTFC_en_b		= 0,
	ETHINTFC_en_m		= 0x00000001,
	ETHINTFC_its_b		= 1,
	ETHINTFC_its_m		= 0x00000002,
	ETHINTFC_rip_b		= 2,
	ETHINTFC_rip_m		= 0x00000004,
	ETHINTFC_jam_b		= 3,
	ETHINTFC_jam_m		= 0x00000008,
	ETHINTFC_ovr_b		= 4,
	ETHINTFC_ovr_m		= 0x00000010,
	ETHINTFC_und_b		= 5,
	ETHINTFC_und_m		= 0x00000020,

	ETHFIFOTT_tth_b		= 0,
	ETHFIFOTT_tth_m		= 0x0000007f,

	ETHARC_pro_b		= 0,
	ETHARC_pro_m		= 0x00000001,
	ETHARC_am_b		= 1,
	ETHARC_am_m		= 0x00000002,
	ETHARC_afm_b		= 2,
	ETHARC_afm_m		= 0x00000004,
	ETHARC_ab_b		= 3,
	ETHARC_ab_m		= 0x00000008,

	ETHSAL_byte5_b		= 0,
	ETHSAL_byte5_m		= 0x000000ff,
	ETHSAL_byte4_b		= 8,
	ETHSAL_byte4_m		= 0x0000ff00,
	ETHSAL_byte3_b		= 16,
	ETHSAL_byte3_m		= 0x00ff0000,
	ETHSAL_byte2_b		= 24,
	ETHSAL_byte2_m		= 0xff000000,

	ETHSAH_byte1_b		= 0,
	ETHSAH_byte1_m		= 0x000000ff,
	ETHSAH_byte0_b		= 8,
	ETHSAH_byte0_m		= 0x0000ff00,
	
	ETHGPF_ptv_b		= 0,
	ETHGPF_ptv_m		= 0x0000ffff,

	ETHPFS_pfd_b		= 0,
	ETHPFS_pfd_m		= 0x00000001,

	ETHCFSA0_cfsa4_b	= 0,
	ETHCFSA0_cfsa4_m	= 0x000000ff,
	ETHCFSA0_cfsa5_b	= 8,
	ETHCFSA0_cfsa5_m	= 0x0000ff00,

	ETHCFSA1_cfsa2_b	= 0,
	ETHCFSA1_cfsa2_m	= 0x000000ff,
	ETHCFSA1_cfsa3_b	= 8,
	ETHCFSA1_cfsa3_m	= 0x0000ff00,

	ETHCFSA2_cfsa0_b	= 0,
	ETHCFSA2_cfsa0_m	= 0x000000ff,
	ETHCFSA2_cfsa1_b	= 8,
	ETHCFSA2_cfsa1_m	= 0x0000ff00,

	ETHMAC1_re_b		= 0,
	ETHMAC1_re_m		= 0x00000001,
	ETHMAC1_paf_b		= 1,
	ETHMAC1_paf_m		= 0x00000002,
	ETHMAC1_rfc_b		= 2,
	ETHMAC1_rfc_m		= 0x00000004,
	ETHMAC1_tfc_b		= 3,
	ETHMAC1_tfc_m		= 0x00000008,
	ETHMAC1_lb_b		= 4,
	ETHMAC1_lb_m		= 0x00000010,
	ETHMAC1_mr_b		= 31,
	ETHMAC1_mr_m		= 0x80000000,

	ETHMAC2_fd_b		= 0,
	ETHMAC2_fd_m		= 0x00000001,
	ETHMAC2_flc_b		= 1,
	ETHMAC2_flc_m		= 0x00000002,
	ETHMAC2_hfe_b		= 2,
	ETHMAC2_hfe_m		= 0x00000004,
	ETHMAC2_dc_b		= 3,
	ETHMAC2_dc_m		= 0x00000008,
	ETHMAC2_cen_b		= 4,
	ETHMAC2_cen_m		= 0x00000010,
	ETHMAC2_pe_b		= 5,
	ETHMAC2_pe_m		= 0x00000020,
	ETHMAC2_vpe_b		= 6,
	ETHMAC2_vpe_m		= 0x00000040,
	ETHMAC2_ape_b		= 7,
	ETHMAC2_ape_m		= 0x00000080,
	ETHMAC2_ppe_b		= 8,
	ETHMAC2_ppe_m		= 0x00000100,
	ETHMAC2_lpe_b		= 9,
	ETHMAC2_lpe_m		= 0x00000200,
	ETHMAC2_nb_b		= 12,
	ETHMAC2_nb_m		= 0x00001000,
	ETHMAC2_bp_b		= 13,
	ETHMAC2_bp_m		= 0x00002000,
	ETHMAC2_ed_b		= 14,
	ETHMAC2_ed_m		= 0x00004000,

	ETHIPGT_ipgt_b		= 0,
	ETHIPGT_ipgt_m		= 0x0000007f,

	ETHIPGR_ipgr2_b		= 0,
	ETHIPGR_ipgr2_m		= 0x0000007f,
	ETHIPGR_ipgr1_b		= 8,
	ETHIPGR_ipgr1_m		= 0x00007f00,

	ETHCLRT_maxret_b	= 0,
	ETHCLRT_maxret_m	= 0x0000000f,
	ETHCLRT_colwin_b	= 8,
	ETHCLRT_colwin_m	= 0x00003f00,

	ETHMAXF_maxf_b		= 0,
	ETHMAXF_maxf_m		= 0x0000ffff,

	ETHMTEST_tb_b		= 2,
	ETHMTEST_tb_m		= 0x00000004,

	ETHMCP_div_b		= 0,
	ETHMCP_div_m		= 0x000000ff,
	
	MIIMCFG_rsv_b		= 0,
	MIIMCFG_rsv_m		= 0x0000000c,

	MIIMCMD_rd_b		= 0,
	MIIMCMD_rd_m		= 0x00000001,
	MIIMCMD_scn_b		= 1,
	MIIMCMD_scn_m		= 0x00000002,

	MIIMADDR_regaddr_b	= 0,
	MIIMADDR_regaddr_m	= 0x0000001f,
	MIIMADDR_phyaddr_b	= 8,
	MIIMADDR_phyaddr_m	= 0x00001f00,

	MIIMWTD_wdata_b		= 0,
	MIIMWTD_wdata_m		= 0x0000ffff,

	MIIMRDD_rdata_b		= 0,
	MIIMRDD_rdata_m		= 0x0000ffff,

	MIIMIND_bsy_b		= 0,
	MIIMIND_bsy_m		= 0x00000001,
	MIIMIND_scn_b		= 1,
	MIIMIND_scn_m		= 0x00000002,
	MIIMIND_nv_b		= 2,
	MIIMIND_nv_m		= 0x00000004,

} ;

/*
 * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
 */
enum
{
	ETHRX_fd_b		= 0,
	ETHRX_fd_m		= 0x00000001,
	ETHRX_ld_b		= 1,
	ETHRX_ld_m		= 0x00000002,
	ETHRX_rok_b		= 2,
	ETHRX_rok_m		= 0x00000004,
	ETHRX_fm_b		= 3,
	ETHRX_fm_m		= 0x00000008,
	ETHRX_mp_b		= 4,
	ETHRX_mp_m		= 0x00000010,
	ETHRX_bp_b		= 5,
	ETHRX_bp_m		= 0x00000020,
	ETHRX_vlt_b		= 6,
	ETHRX_vlt_m		= 0x00000040,
	ETHRX_cf_b		= 7,
	ETHRX_cf_m		= 0x00000080,
	ETHRX_ovr_b		= 8,
	ETHRX_ovr_m		= 0x00000100,
	ETHRX_crc_b		= 9,
	ETHRX_crc_m		= 0x00000200,
	ETHRX_cv_b		= 10,
	ETHRX_cv_m		= 0x00000400,
	ETHRX_db_b		= 11,
	ETHRX_db_m		= 0x00000800,
	ETHRX_le_b		= 12,
	ETHRX_le_m		= 0x00001000,
	ETHRX_lor_b		= 13,
	ETHRX_lor_m		= 0x00002000,
	ETHRX_ces_b		= 14,
	ETHRX_ces_m		= 0x00004000,
	ETHRX_length_b		= 16,
	ETHRX_length_m		= 0xffff0000,

	ETHTX_fd_b		= 0,
	ETHTX_fd_m		= 0x00000001,
	ETHTX_ld_b		= 1,
	ETHTX_ld_m		= 0x00000002,
	ETHTX_oen_b		= 2,
	ETHTX_oen_m		= 0x00000004,
	ETHTX_pen_b		= 3,
	ETHTX_pen_m		= 0x00000008,
	ETHTX_cen_b		= 4,
	ETHTX_cen_m		= 0x00000010,
	ETHTX_hen_b		= 5,
	ETHTX_hen_m		= 0x00000020,
	ETHTX_tok_b		= 6,
	ETHTX_tok_m		= 0x00000040,
	ETHTX_mp_b		= 7,
	ETHTX_mp_m		= 0x00000080,
	ETHTX_bp_b		= 8,
	ETHTX_bp_m		= 0x00000100,
	ETHTX_und_b		= 9,
	ETHTX_und_m		= 0x00000200,
	ETHTX_of_b		= 10,
	ETHTX_of_m		= 0x00000400,
	ETHTX_ed_b		= 11,
	ETHTX_ed_m		= 0x00000800,
	ETHTX_ec_b		= 12,
	ETHTX_ec_m		= 0x00001000,
	ETHTX_lc_b		= 13,
	ETHTX_lc_m		= 0x00002000,
	ETHTX_td_b		= 14,
	ETHTX_td_m		= 0x00004000,
	ETHTX_crc_b		= 15,
	ETHTX_crc_m		= 0x00008000,
	ETHTX_le_b		= 16,
	ETHTX_le_m		= 0x00010000,
	ETHTX_cc_b		= 17,
	ETHTX_cc_m		= 0x001E0000,
} ;

#endif	// __IDT_ETH_H__