tx4925.h

for mips adm5120 uclibc-0.9.19 toolchain

#ifndef TX4925_TX4925_H
#define TX4925_TX4925_H

/*
 * linux/include/asm-mips/tx4925/tx4925.h
 *
 * tx4925 defs
 *
 * Author: MontaVista Software, Inc.  [e-mail]
 *
 * Copyright 2001-2002 MontaVista Software Inc.
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <asm/tx4925/tx4925_mips.h>

/*
 This register naming came from the intergrate cpu/controoler name TX4925
 followed by the device name from table 4.2.2 on page 4-3 and then followed
 by the register name from table 4.2.3 on pages 4-4 to 4-8.  The manaul
 used is "TMPR4925BT Preliminary Rev 0.1 20.Jul.2001".
 */

/* TX4925 controller */
#define TX4925_BASE                     0xff1f0000
#define TX4925_LIMIT                    0xff1fffff

#define TX4925_MKA(x) ((u32)( ((u32)(TX4925_BASE)) | ((u32)(x)) ))

/* TX4925 SDRAM controller (64-bit registers) */
#define TX4925_SDRAMC_BASE              0x8000
#define TX4925_SDRAMC_SDCCR0            0x8000
#define TX4925_SDRAMC_SDCCR1            0x8008
#define TX4925_SDRAMC_SDCCR2            0x8010
#define TX4925_SDRAMC_SDCCR3            0x8018
#define TX4925_SDRAMC_SDCTR             0x8040
#define TX4925_SDRAMC_SDCMD             0x8058
#define TX4925_SDRAMC_LIMIT             0x8fff

/* TX4925 external bus controller (64-bit registers) */
#define TX4925_EBUSC_BASE               0x9000
#define TX4925_EBUSC_EBCCR0             0x9000
#define TX4925_EBUSC_EBBAR0             0x9004
#define TX4925_EBUSC_EBCCR1             0x9008
#define TX4925_EBUSC_EBBAR1             0x900c
#define TX4925_EBUSC_EBCCR2             0x9010
#define TX4925_EBUSC_EBBAR2             0x9014
#define TX4925_EBUSC_EBCCR3             0x9018
#define TX4925_EBUSC_EBBAR3             0x901c
#define TX4925_EBUSC_EBCCR4             0x9020
#define TX4925_EBUSC_EBBAR4             0x9024
#define TX4925_EBUSC_EBCCR5             0x9028
#define TX4925_EBUSC_EBBAR5             0x902c
#define TX4925_EBUSC_EBCCR6             0x9030
#define TX4925_EBUSC_EBBAR6             0x9034
#define TX4925_EBUSC_EBCCR7             0x9038
#define TX4925_EBUSC_EBBAR7             0x903c
#define TX4925_EBUSC_LIMIT              0x9fff

/* TX4925 SDRRAM Error Check Correction (64-bit registers) */
#define TX4925_ECC_BASE                 0xa000
#define TX4925_ECC_ECCCR                0xa000
#define TX4925_ECC_ECCSR                0xa008
#define TX4925_ECC_LIMIT                0xafff

/* TX4925 DMA Controller (64-bit registers) */
#define TX4925_DMAC_BASE                0xb000
#define TX4925_DMAC_TBD                 0xb000
#define TX4925_DMAC_LIMIT               0xbfff

/* TX4925 NAND Flash Memory Controller (32-bit registers) */
#define TX4925_NDFMC_BASE               0xc000
#define TX4925_NDFMC_NDFDTR             0xc000
#define TX4925_NDFMC_NDFMCR             0xc004
#define TX4925_NDFMC_NDFSR              0xc008
#define TX4925_NDFMC_NDFISR             0xc00c
#define TX4925_NDFMC_NDFIMR             0xc010
#define TX4925_NDFMC_NDFSPR             0xc014
#define TX4925_NDFMC_NDFRSTR            0xc018

/* TX4925 PCI Controller (32-bit registers) */
#define TX4925_PCIC_BASE                0xd000
#define TX4925_PCIC_TBD                 0xb000
#define TX4925_PCIC_LIMIT               0xdfff

/* TX4925 Configuration registers (64-bit registers) */
#define TX4925_CONFIG_BASE                       0xe000
#define TX4925_CONFIG_CCFG                       0xe000
#define TX4925_CONFIG_CCFG_RESERVED_26_31                BM_31_26
#define TX4925_CONFIG_CCFG_RF                            BM_25_24
#define TX4925_CONFIG_CCFG_BOOTME                        BM_23_21
#define TX4925_CONFIG_CCFG_PCIMODE                       BM_20_20
#define TX4925_CONFIG_CCFG_RESERVED_18_19                BM_19_18
#define TX4925_CONFIG_CCFG_TINTDIS                       BM_17_17
#define TX4925_CONFIG_CCFG_BEOW                          BM_16_16
#define TX4925_CONFIG_CCFG_WR                            BM_15_15
#define TX4925_CONFIG_CCFG_TOE                           BM_14_14
#define TX4925_CONFIG_CCFG_PCIARB                        BM_13_13
#define TX4925_CONFIG_CCFG_RESERVED_08_12                BM_12_08
#define TX4925_CONFIG_CCFG_SYSSP                         BM_07_06
#define TX4925_CONFIG_CCFG_RESERVED_04_05                BM_05_04
#define TX4925_CONFIG_CCFG_PCTRCE                        BM_03_03
#define TX4925_CONFIG_CCFG_ENDIAN                        BM_02_02
#define TX4925_CONFIG_CCFG_WDRST                         BM_01_01
#define TX4925_CONFIG_CCFG_UAEHOLD                       BM_00_00

#define TX4925_CONFIG_REVID                      0xe004
#define TX4925_CONFIG_REVID_PCODE                        BM_16_31
#define TX4925_CONFIG_REVID_MJERREV                      BM_12_15
#define TX4925_CONFIG_REVID_MINEREV                      BM_08_11
#define TX4925_CONFIG_REVID_MJREV                        BM_04_07
#define TX4925_CONFIG_REVID_MINREV                       BM_00_03
#define TX4925_CONFIG_PCFG                       0xe008
#define TX4925_CONFIG_PCFG_SYSCLKEN                      BM_31_31
#define TX4925_CONFIG_PCFG_SDRCLKEN                      BM_30_29
#define TX4925_CONFIG_PCFG_PCICLKEN                      BM_28_27
#define TX4925_CONFIG_PCFG_PCICLKIOEN                    BM_26_26
#define TX4925_CONFIG_PCFG_RESERVED_22_25                BM_25_22
#define TX4925_CONFIG_PCFG_SELSPL                        BM_21_21
#define TX4925_CONFIG_PCFG_SELCHI                        BM_20_20
#define TX4925_CONFIG_PCFG_SELCARD                       BM_19_18
#define TX4925_CONFIG_PCFG_SELCE                         BM_17_16
#define TX4925_CONFIG_PCFG_SELSIOC                       BM_15_14
#define TX4925_CONFIG_PCFG_SELSIO                        BM_13_12
#define TX4925_CONFIG_PCFG_ACKIN                         BM_11_11
#define TX4925_CONFIG_PCFG_SELTMR                        BM_10_09
#define TX4925_CONFIG_PCFG_SELDONE                       BM_08_08
#define TX4925_CONFIG_PCFG_RESERVED_04_07                BM_07_04
#define TX4925_CONFIG_PCFG_SELACLC                       BM_03_03
#define TX4925_CONFIG_PCFG_SELNAND                       BM_02_02
#define TX4925_CONFIG_PCFG_SELDMA                        BM_01_00
#define TX4925_CONFIG_TOEA                       0xe00c
#define TX4925_CONFIG_TOEA_TOEA                          BM_00_31
#define TX4925_CONFIG_CLKCTR                     0xe028
#define TX4925_CONFIG_CLKCTR_RESERVED_28_31              BM_31_28
#define TX4925_CONFIG_CLKCTR_PCICKE                      BM_27_27
#define TX4925_CONFIG_CLKCTR_DMACKE                      BM_26_26
#define TX4925_CONFIG_CLKCTR_RESERVED_25_25              BM_25_25
#define TX4925_CONFIG_CLKCTR_SIO0CKE                     BM_24_24
#define TX4925_CONFIG_CLKCTR_SIO1CKE                     BM_23_23
#define TX4925_CONFIG_CLKCTR_TMR0CKE                     BM_22_22
#define TX4925_CONFIG_CLKCTR_TMR1CKE                     BM_21_21
#define TX4925_CONFIG_CLKCTR_TMR2CKE                     BM_20_20
#define TX4925_CONFIG_CLKCTR_CHICKE                      BM_19_19
#define TX4925_CONFIG_CLKCTR_SPICKE                      BM_18_18
#define TX4925_CONFIG_CLKCTR_ACLCKE                      BM_17_17
#define TX4925_CONFIG_CLKCTR_PIOCKE                      BM_16_16
#define TX4925_CONFIG_CLKCTR_RESERVED_12_15              BM_15_12
#define TX4925_CONFIG_CLKCTR_PCIRSTI                     BM_11_11
#define TX4925_CONFIG_CLKCTR_DMARSTI                     BM_10_10
#define TX4925_CONFIG_CLKCTR_RESERVED_09_09              BM_09_09
#define TX4925_CONFIG_CLKCTR_SIO0RSTI                    BM_08_08
#define TX4925_CONFIG_CLKCTR_SIO1RSTI                    BM_07_07
#define TX4925_CONFIG_CLKCTR_TMR0RSTI                    BM_06_06
#define TX4925_CONFIG_CLKCTR_TMR1RSTI                    BM_05_05
#define TX4925_CONFIG_CLKCTR_TMR2RSTI                    BM_04_04
#define TX4925_CONFIG_CLKCTR_CHIRSTI                     BM_03_03
#define TX4925_CONFIG_CLKCTR_SPIRSTI                     BM_02_02
#define TX4925_CONFIG_CLKCTR_ACLRSTI                     BM_01_01
#define TX4925_CONFIG_CLKCTR_PIORSTI                     BM_00_00
#define TX4925_CONFIG_GARBC                      0xe02c
#define TX4925_CONFIG_GARBC_RESERVED_04_31               BM_31_04
#define TX4925_CONFIG_GARBC_ARBMD                        BM_03_00
#define TX4925_CONFIG_RAMP                       0xe030
#define TX4925_CONFIG_RAMP_RESERVED_16_31                BM_31_16
#define TX4925_CONFIG_RAMP_RAMP                          BM_15_00
#define TX4925_CONFIG_LIMIT                      0xe034

/* TX4925 Timer 0 (32-bit registers) */
#define TX4925_TMR0_BASE                0xf000
#define TX4925_TMR0_TMTCR0              0xf004
#define TX4925_TMR0_TMTISR0             0xf008
#define TX4925_TMR0_TMCPRA0             0xf008
#define TX4925_TMR0_TMCPRB0             0xf00c
#define TX4925_TMR0_TMITMR0             0xf010
#define TX4925_TMR0_TMCCDR0             0xf020
#define TX4925_TMR0_TMPGMR0             0xf030
#define TX4925_TMR0_TMTRR0              0xf0f0
#define TX4925_TMR0_LIMIT               0xf0ff

/* TX4925 Timer 1 (32-bit registers) */
#define TX4925_TMR1_BASE                0xf100
#define TX4925_TMR1_TMTCR1              0xf104
#define TX4925_TMR1_TMTISR1             0xf108
#define TX4925_TMR1_TMCPRA1             0xf108
#define TX4925_TMR1_TMCPRB1             0xf10c
#define TX4925_TMR1_TMITMR1             0xf110
#define TX4925_TMR1_TMCCDR1             0xf120
#define TX4925_TMR1_TMPGMR1             0xf130
#define TX4925_TMR1_TMTRR1              0xf1f0
#define TX4925_TMR1_LIMIT               0xf1ff

/* TX4925 Timer 2 (32-bit registers) */
#define TX4925_TMR2_BASE                0xf200
#define TX4925_TMR2_TMTCR2              0xf104
#define TX4925_TMR2_TMTISR2             0xf208
#define TX4925_TMR2_TMCPRA2             0xf208
#define TX4925_TMR2_TMCPRB2             0xf20c
#define TX4925_TMR2_TMITMR2             0xf210
#define TX4925_TMR2_TMCCDR2             0xf220
#define TX4925_TMR2_TMPGMR2             0xf230
#define TX4925_TMR2_TMTRR2              0xf2f0
#define TX4925_TMR2_LIMIT               0xf2ff

/* TX4925 serial port 0 (32-bit registers) */
#define TX4925_SIO0_BASE                         0xf300
#define TX4925_SIO0_SILCR0                       0xf300
#define TX4925_SIO0_SILCR0_RESERVED_16_31                BM_16_31
#define TX4925_SIO0_SILCR0_RWUB                          BM_15_15
#define TX4925_SIO0_SILCR0_TWUB                          BM_14_14
#define TX4925_SIO0_SILCR0_UODE                          BM_13_13
#define TX4925_SIO0_SILCR0_RESERVED_07_12                BM_07_12
#define TX4925_SIO0_SILCR0_SCS                           BM_05_06
#define TX4925_SIO0_SILCR0_SCS_IMBUSCLK_IC             (~BM_05_06)
#define TX4925_SIO0_SILCR0_SCS_IMBUSCLK_BRG              BM_05_05
#define TX4925_SIO0_SILCR0_SCS_SCLK_EC                   BM_06_06
#define TX4925_SIO0_SILCR0_SCS_SCLK_BRG                  BM_05_06
#define TX4925_SIO0_SILCR0_UEPS                          BM_04_04
#define TX4925_SIO0_SILCR0_UPEN                          BM_03_03
#define TX4925_SIO0_SILCR0_USBL                          BM_02_02
#define TX4925_SIO0_SILCR0_UMODE                         BM_00_01
#define TX4925_SIO0_SILCR0_UMODE_DATA_8_BIT              BM_00_01
#define TX4925_SIO0_SILCR0_UMODE_DATA_7_BIT            (~BM_00_01)