rc32355_eth.h

for mips adm5120 uclibc-0.9.19 toolchain

/*
 *
 * BRIEF MODULE DESCRIPTION
 *      Ethernet registers on IDT RC32355 (Banyan)
 *
 * Author: Steve Longerbeam <[e-mail], or [e-mail]>
 *
 * 2002 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#ifndef BANYAN_ETHER_H
#define BANYAN_ETHER_H

#include <asm/rc32300/rc32355_dma.h>

/*
 * A partial image of the RC32355 ethernet registers
 */
typedef struct {
	u32 ethintfc;
	u32 ethfifott;
	u32 etharc;
	u32 ethhash0;
	u32 ethhash1;
	u32 ethfifost;
	u32 ethfifos;
	u32 ethodeops;
	u32 ethis;
	u32 ethos;
	u32 ethmcp;
	u32 _u1;
	u32 ethid;
	u32 _u2;
	u32 _u3;
	u32 _u4;
	u32 ethod;
	u32 _u5;
	u32 _u6;
	u32 _u7;
	u32 ethodeop;
	u32 _u8[43]; 
	u32 ethsal0;
	u32 ethsah0;
	u32 ethsal1;
	u32 ethsah1;
	u32 ethsal2;
	u32 ethsah2;
	u32 ethsal3;
	u32 ethsah3;
	u32 ethrbc;
	u32 ethrpc;
	u32 ethrupc;
	u32 ethrfc;
	u32 ethtbc;
	u32 ethgpf;
	u32 _u9[50];
	u32 ethmac1;
	u32 ethmac2;
	u32 ethipgt;
	u32 ethipgr;
	u32 ethclrt;
	u32 ethmaxf;
	u32 _u10;
	u32 ethmtest;
	u32 miimcfg;
	u32 miimcmd;
	u32 miimaddr;
	u32 miimwtd;
	u32 miimrdd;
	u32 miimind;
	u32 _u11;
	u32 _u12;
	u32 ethcfsa0;
	u32 ethcfsa1;
	u32 ethcfsa2;
} rc32355_eth_regs_t;
 
#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))

#define ETH_INTFC   (RC32355_ETH_BASE + 0x000) /* INTerFace Control  */
#define ETH_FIFOTT  (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold  */
#define ETH_ARC     (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl  */
#define ETH_HASH0   (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
#define ETH_HASH1   (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
#define ETH_FIFOST  (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
#define ETH_FIFOS   (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
#define ETH_ODEOPS  (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
#define ETH_IS      (RC32355_ETH_BASE + 0x020) /* Input Status */
#define ETH_OS      (RC32355_ETH_BASE + 0x024) /* Output Status  */
#define ETH_MCP     (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
#define ETH_ID      (RC32355_ETH_BASE + 0x030) /* Input Data register */
#define ETH_OD      (RC32355_ETH_BASE + 0x040) /* Output Data register */
#define ETH_ODEOP   (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */

/* for n in { 0, 1, 2, 3 } */
#define ETH_SAL(n)  (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
#define ETH_SAH(n)  (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */

#define ETH_RBC     (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
#define ETH_RPC     (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
#define ETH_RUPC    (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
#define ETH_RFC     (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
#define ETH_TBC     (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
#define ETH_GPF     (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
#define ETH_MAC1    (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
#define ETH_MAC2    (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
#define ETH_IPGT    (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
#define ETH_IPGR    (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
#define ETH_CLRT    (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
#define ETH_MAXF    (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
#define ETH_MTEST   (RC32355_ETH_BASE + 0x21C) /* MAC Test */

#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command  */
#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */

/* for n in { 0, 1, 2 } */
#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4))  /* Station Addr */


/*
 * Register Interpretations follow
 */

/******************************************************************************
 * ETHINTFC register
 *****************************************************************************/

#define ETHERINTFC_EN            (1<<0)
#define ETHERINTFC_ITS           (1<<1)
#define ETHERINTFC_RES           (1<<2)
#define ETHERINTFC_RIP           (1<<2)
#define ETHERINTFC_JAM           (1<<3)

/******************************************************************************
 * ETHFIFOTT register
 *****************************************************************************/

#define ETHERFIFOTT_TTH(v)      (((v)&0x3f)<<0)

/******************************************************************************
 * ETHARC register
 *****************************************************************************/

#define ETHERARC_PRO             (1<<0)
#define ETHERARC_AM              (1<<1)
#define ETHERARC_AFM             (1<<2)
#define ETHERARC_AB              (1<<3)

/******************************************************************************
 * ETHHASH registers
 *****************************************************************************/

#define ETHERHASH0(v)            (((v)&0xffff)<<0)
#define ETHERHASH1(v)            (((v)&0xffff)<<0)

/******************************************************************************
 * ETHSA registers
 *****************************************************************************/

#define ETHERSAL0(v)             (((v)&0xffff)<<0)
#define ETHERSAL1(v)             (((v)&0xffff)<<0)
#define ETHERSAL2(v)             (((v)&0xffff)<<0)
#define ETHERSAL3(v)             (((v)&0xffff)<<0)
#define ETHERSAH0(v)             (((v)&0xff)<<0)
#define ETHERSAH1(v)             (((v)&0xff)<<0)
#define ETHERSAH2(v)             (((v)&0xff)<<0)
#define ETHERSAH3(v)             (((v)&0xff)<<0)

/******************************************************************************
 * ETHFIFOST register
 *****************************************************************************/

#define ETHERFIFOST_IRTH(v)      (((v)&0x3f)<<0)
#define ETHERFIFOST_ORTH(v)      (((v)&0x3f)<<16)

/******************************************************************************
 * ETHFIFOS register
 *****************************************************************************/

#define ETHERFIFOS_IR            (1<<0)
#define ETHERFIFOS_OR            (1<<1)  
#define ETHERFIFOS_OVR           (1<<2)  
#define ETHERFIFOS_UND           (1<<3)  

/******************************************************************************
 * DATA registers
 *****************************************************************************/

#define ETHERID(v)               (((v)&0xffff)<<0)
#define ETHEROD(v)               (((v)&0xffff)<<0)

/******************************************************************************
 * ETHODEOPS register
 *****************************************************************************/

#define ETHERODEOPS_SIZE(v)      (((v)&0x3)<<0)

/******************************************************************************
 * ETHODEOP register
 *****************************************************************************/

#define ETHERODEOP(v)            (((v)&0xffff)<<0)