linux-2.6.12-rc4-mips-headers.patch

mips-nptl patches for crosstool-0.34

diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/bootinfo.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/bootinfo.h
--- linux-2.6.12-rc4/include/asm-mips/bootinfo.h	2005-04-27 13:23:30.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/bootinfo.h	2005-03-02 20:14:42.205787706 -0600
@@ -177,6 +177,8 @@
 #define  MACH_MTX1		7       /* 4G MTX-1 Au1500-based board */
 #define  MACH_PB1550		8       /* Au1550-based eval board */
 #define  MACH_DB1550		9       /* Au1550-based eval board */
+#define  MACH_PB1200		10       /* Au1200-based eval board */
+#define  MACH_DB1200		11       /* Au1200-based eval board */
 
 /*
  * Valid machtype for group NEC_VR41XX
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/break.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/break.h
--- linux-2.6.12-rc4/include/asm-mips/break.h	2005-04-27 13:23:30.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/break.h	2005-02-18 23:04:56.029192784 -0600
@@ -28,6 +28,7 @@
 #define BRK_NORLD	10	/* No rld found - not used by Linux/MIPS */
 #define _BRK_THREADBP	11	/* For threads, user bp (used by debuggers) */
 #define BRK_BUG		512	/* Used by BUG() */
+#define BRK_KDB		513	/* Used in KDB_ENTER() */
 #define BRK_MULOVF	1023	/* Multiply overflow */
 
 #endif /* __ASM_BREAK_H */
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/bug.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/bug.h
--- linux-2.6.12-rc4/include/asm-mips/bug.h	2005-05-20 16:18:24.082258804 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/bug.h	2005-05-20 16:08:51.931523392 -0500
@@ -1,16 +1,21 @@
 #ifndef __ASM_BUG_H
 #define __ASM_BUG_H
 
-#include <asm/break.h>
+#include <linux/config.h>
 
 #ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
+
+#include <asm/break.h>
+
 #define BUG()								\
 do {									\
 	__asm__ __volatile__("break %0" : : "i" (BRK_BUG));		\
 } while (0)
+
+#define HAVE_ARCH_BUG
+
 #endif
 
 #include <asm-generic/bug.h>
 
-#endif
+#endif /* __ASM_BUG_H */
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/bugs.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/bugs.h
--- linux-2.6.12-rc4/include/asm-mips/bugs.h	2004-10-18 16:54:37.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/bugs.h	2005-04-13 19:47:08.455662860 -0500
@@ -8,12 +8,18 @@
 #define _ASM_BUGS_H
 
 #include <linux/config.h>
+#include <linux/delay.h>
+#include <asm/cpu.h>
+#include <asm/cpu-info.h>
 
 extern void check_bugs32(void);
 extern void check_bugs64(void);
 
 static inline void check_bugs(void)
 {
+	unsigned int cpu = smp_processor_id();
+
+	cpu_data[cpu].udelay_val = loops_per_jiffy;
 	check_bugs32();
 #ifdef CONFIG_MIPS64
 	check_bugs64();
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/cacheflush.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cacheflush.h
--- linux-2.6.12-rc4/include/asm-mips/cacheflush.h	2005-05-20 16:18:24.083258634 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cacheflush.h	2005-04-27 14:32:28.692140052 -0500
@@ -49,17 +49,29 @@
 
 extern void (*flush_icache_page)(struct vm_area_struct *vma,
 	struct page *page);
-extern void (*flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*flush_icache_range)(unsigned long __user start,
+	unsigned long __user end);
 #define flush_cache_vmap(start, end)		flush_cache_all()
 #define flush_cache_vunmap(start, end)		flush_cache_all()
 
-#define copy_to_user_page(vma, page, vaddr, dst, src, len)		\
-do {									\
-	memcpy(dst, (void *) src, len);					\
-	flush_icache_page(vma, page);					\
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)		\
-	memcpy(dst, src, len)
+static inline void copy_to_user_page(struct vm_area_struct *vma,
+	struct page *page, unsigned long vaddr, void *dst, const void *src,
+	unsigned long len)
+{
+	if (cpu_has_dc_aliases)
+		flush_cache_page(vma, vaddr, page_to_pfn(page));
+	memcpy(dst, src, len);
+	flush_icache_page(vma, page);
+}
+
+static inline void copy_from_user_page(struct vm_area_struct *vma,
+	struct page *page, unsigned long vaddr, void *dst, const void *src,
+	unsigned long len)
+{
+	if (cpu_has_dc_aliases)
+		flush_cache_page(vma, vaddr, page_to_pfn(page));
+	memcpy(dst, src, len);
+}
 
 extern void (*flush_cache_sigtramp)(unsigned long addr);
 extern void (*flush_icache_all)(void);
@@ -78,4 +90,7 @@
 #define ClearPageDcacheDirty(page)	\
 	clear_bit(PG_dcache_dirty, &(page)->flags)
 
+/* Run kernel code uncached, useful for cache probing functions. */
+unsigned long __init run_uncached(void *func);
+
 #endif /* _ASM_CACHEFLUSH_H */
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/cobalt/cobalt.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cobalt/cobalt.h
--- linux-2.6.12-rc4/include/asm-mips/cobalt/cobalt.h	2004-10-18 16:53:13.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cobalt/cobalt.h	2005-04-13 19:47:08.994575168 -0500
@@ -19,18 +19,23 @@
  *     9  - PCI
  *    14  - IDE0
  *    15  - IDE1
- *
+ */
+#define COBALT_QUBE_SLOT_IRQ	9
+
+/*
  * CPU IRQs  are 16 ... 23
  */
-#define COBALT_TIMER_IRQ	18
-#define COBALT_SCC_IRQ          19		/* pre-production has 85C30 */
-#define COBALT_RAQ_SCSI_IRQ	19
-#define COBALT_ETH0_IRQ		19
-#define COBALT_ETH1_IRQ		20
-#define COBALT_SERIAL_IRQ	21
-#define COBALT_SCSI_IRQ         21
-#define COBALT_VIA_IRQ		22		/* Chained to VIA ISA bridge */
-#define COBALT_QUBE_SLOT_IRQ	23
+#define COBALT_CPU_IRQ		16
+
+#define COBALT_GALILEO_IRQ	(COBALT_CPU_IRQ + 2)
+#define COBALT_SCC_IRQ          (COBALT_CPU_IRQ + 3)	/* pre-production has 85C30 */
+#define COBALT_RAQ_SCSI_IRQ	(COBALT_CPU_IRQ + 3)
+#define COBALT_ETH0_IRQ		(COBALT_CPU_IRQ + 3)
+#define COBALT_QUBE1_ETH0_IRQ	(COBALT_CPU_IRQ + 4)
+#define COBALT_ETH1_IRQ		(COBALT_CPU_IRQ + 4)
+#define COBALT_SERIAL_IRQ	(COBALT_CPU_IRQ + 5)
+#define COBALT_SCSI_IRQ         (COBALT_CPU_IRQ + 5)
+#define COBALT_VIA_IRQ		(COBALT_CPU_IRQ + 6)	/* Chained to VIA ISA bridge */
 
 /*
  * PCI configuration space manifest constants.  These are wired into
@@ -69,16 +74,21 @@
  * Most of this really should go into a separate GT64111 header file.
  */
 #define GT64111_IO_BASE		0x10000000UL
+#define GT64111_IO_END		0x11ffffffUL
+#define GT64111_MEM_BASE	0x12000000UL
+#define GT64111_MEM_END		0x13ffffffUL
 #define GT64111_BASE		0x14000000UL
-#define GALILEO_REG(ofs)	(KSEG0 + GT64111_BASE + (unsigned long)(ofs))
+#define GALILEO_REG(ofs)	CKSEG1ADDR(GT64111_BASE + (unsigned long)(ofs))
 
 #define GALILEO_INL(port)	(*(volatile unsigned int *) GALILEO_REG(port))
 #define GALILEO_OUTL(val, port)						\
 do {									\
-	*(volatile unsigned int *) GALILEO_REG(port) = (port);		\
+	*(volatile unsigned int *) GALILEO_REG(port) = (val);		\
 } while (0)
 
-#define GALILEO_T0EXP		0x0100
+#define GALILEO_INTR_T0EXP	(1 << 8)
+#define GALILEO_INTR_RETRY_CTR	(1 << 20)
+
 #define GALILEO_ENTC0		0x01
 #define GALILEO_SELTC0		0x02
 
@@ -86,5 +96,21 @@
 	GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) |		\
 		(PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
 
+#define COBALT_LED_PORT		(*(volatile unsigned char *) CKSEG1ADDR(0x1c000000))
+# define COBALT_LED_BAR_LEFT	(1 << 0)	/* Qube */
+# define COBALT_LED_BAR_RIGHT	(1 << 1)	/* Qube */
+# define COBALT_LED_WEB		(1 << 2)	/* RaQ */
+# define COBALT_LED_POWER_OFF	(1 << 3)	/* RaQ */
+# define COBALT_LED_RESET	0x0f
+
+#define COBALT_KEY_PORT		((~*(volatile unsigned int *) CKSEG1ADDR(0x1d000000) >> 24) & COBALT_KEY_MASK)
+# define COBALT_KEY_CLEAR	(1 << 1)
+# define COBALT_KEY_LEFT	(1 << 2)
+# define COBALT_KEY_UP		(1 << 3)
+# define COBALT_KEY_DOWN	(1 << 4)
+# define COBALT_KEY_RIGHT	(1 << 5)
+# define COBALT_KEY_ENTER	(1 << 6)
+# define COBALT_KEY_SELECT	(1 << 7)
+# define COBALT_KEY_MASK	0xfe
 
 #endif /* __ASM_COBALT_H */
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/cobalt/mach-gt64120.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cobalt/mach-gt64120.h
--- linux-2.6.12-rc4/include/asm-mips/cobalt/mach-gt64120.h	1969-12-31 18:00:00.000000000 -0600
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cobalt/mach-gt64120.h	2005-02-21 10:24:02.000000000 -0600
@@ -0,0 +1 @@
+/* there's something here ... in the dark */
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/cpu-features.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cpu-features.h
--- linux-2.6.12-rc4/include/asm-mips/cpu-features.h	2005-04-27 13:23:30.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cpu-features.h	2005-05-05 20:48:02.574948859 -0500
@@ -4,6 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef __ASM_CPU_FEATURES_H
 #define __ASM_CPU_FEATURES_H
@@ -39,9 +40,6 @@
 #ifndef cpu_has_watch
 #define cpu_has_watch		(cpu_data[0].options & MIPS_CPU_WATCH)
 #endif
-#ifndef cpu_has_mips16
-#define cpu_has_mips16		(cpu_data[0].options & MIPS_CPU_MIPS16)
-#endif
 #ifndef cpu_has_divec
 #define cpu_has_divec		(cpu_data[0].options & MIPS_CPU_DIVEC)
 #endif
@@ -66,6 +64,18 @@
 #ifndef cpu_has_llsc
 #define cpu_has_llsc		(cpu_data[0].options & MIPS_CPU_LLSC)
 #endif
+#ifndef cpu_has_mips16
+#define cpu_has_mips16		(cpu_data[0].ases & MIPS_ASE_MIPS16)
+#endif
+#ifndef cpu_has_mdmx
+#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#endif
+#ifndef cpu_has_mips3d
+#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#endif
+#ifndef cpu_has_smartmips
+#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/cpu-info.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cpu-info.h
--- linux-2.6.12-rc4/include/asm-mips/cpu-info.h	2005-04-27 13:23:30.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cpu-info.h	2005-05-05 20:48:02.582947538 -0500
@@ -7,6 +7,7 @@
  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
  * Copyright (C) 1996 Paul M. Antoine
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef __ASM_CPU_INFO_H
 #define __ASM_CPU_INFO_H
@@ -61,6 +62,7 @@
 	 * Capability and feature descriptor structure for MIPS CPU
 	 */
 	unsigned long		options;
+	unsigned long		ases;
 	unsigned int		processor_id;
 	unsigned int		fpu_id;
 	unsigned int		cputype;
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/cpu.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cpu.h
--- linux-2.6.12-rc4/include/asm-mips/cpu.h	2004-10-18 16:53:21.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/cpu.h	2005-05-05 20:48:02.585947042 -0500
@@ -3,6 +3,7 @@
  *        various MIPS cpu types.
  *
  * Copyright (C) 1996 David S. Miller ([e-mail])
+ * Copyright (C) 2004  Maciej W. Rozycki
  */
 #ifndef _ASM_CPU_H
 #define _ASM_CPU_H
@@ -22,12 +23,17 @@
    spec.
 */
 
-#define PRID_COMP_LEGACY       0x000000
-#define PRID_COMP_MIPS         0x010000
-#define PRID_COMP_BROADCOM     0x020000
-#define PRID_COMP_ALCHEMY      0x030000
-#define PRID_COMP_SIBYTE       0x040000
-#define PRID_COMP_SANDCRAFT    0x050000
+#define PRID_COMP_LEGACY	0x000000
+#define PRID_COMP_MIPS		0x010000
+#define PRID_COMP_BROADCOM	0x020000
+#define PRID_COMP_ALCHEMY	0x030000
+#define PRID_COMP_SIBYTE	0x040000
+#define PRID_COMP_SANDCRAFT	0x050000
+#define PRID_COMP_PHILIPS	0x060000
+#define PRID_COMP_TOSHIBA	0x070000
+#define PRID_COMP_LSI		0x080000
+#define PRID_COMP_LEXRA		0x0b0000
+
 
 /*
  * Assigned values for the product ID register.  In order to detect a
@@ -177,7 +183,8 @@
 #define CPU_VR4133		56
 #define CPU_AU1550		57
 #define CPU_24K			58
-#define CPU_LAST		58
+#define CPU_AU1200		59
+#define CPU_LAST		59
 
 /*
  * ISA Level encodings
@@ -207,7 +214,6 @@
 #define MIPS_CPU_32FPR		0x00000020 /* 32 dbl. prec. FP registers */
 #define MIPS_CPU_COUNTER	0x00000040 /* Cycle count/compare */
 #define MIPS_CPU_WATCH		0x00000080 /* watchpoint registers */
-#define MIPS_CPU_MIPS16		0x00000100 /* code compression */
 #define MIPS_CPU_DIVEC		0x00000200 /* dedicated interrupt vector */
 #define MIPS_CPU_VCE		0x00000400 /* virt. coherence conflict possible */
 #define MIPS_CPU_CACHE_CDEX_P	0x00000800 /* Create_Dirty_Exclusive CACHE op */
@@ -219,4 +225,12 @@
 #define MIPS_CPU_SUBSET_CACHES	0x00020000 /* P-cache subset enforced */
 #define MIPS_CPU_PREFETCH	0x00040000 /* CPU has usable prefetch */
 
+/*
+ * CPU ASE encodings
+ */
+#define MIPS_ASE_MIPS16		0x00000001 /* code compression */
+#define MIPS_ASE_MDMX		0x00000002 /* MIPS digital media extension */
+#define MIPS_ASE_MIPS3D		0x00000004 /* MIPS-3D */
+#define MIPS_ASE_SMARTMIPS	0x00000008 /* SmartMIPS */
+
 #endif /* _ASM_CPU_H */
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/delay.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/delay.h
--- linux-2.6.12-rc4/include/asm-mips/delay.h	2005-04-27 13:21:55.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/delay.h	2005-04-19 18:21:06.803903537 -0500
@@ -12,11 +12,9 @@
 
 #include <linux/config.h>
 #include <linux/param.h>
-
+#include <linux/smp.h>
 #include <asm/compiler.h>
 
-extern unsigned long loops_per_jiffy;
-
 static inline void __delay(unsigned long loops)
 {
 	if (sizeof(long) == 4)
@@ -82,11 +80,7 @@
 	__delay(usecs);
 }
 
-#ifdef CONFIG_SMP
 #define __udelay_val cpu_data[smp_processor_id()].udelay_val
-#else
-#define __udelay_val loops_per_jiffy
-#endif
 
 #define udelay(usecs) __udelay((usecs),__udelay_val)
 
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/dma-mapping.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/dma-mapping.h
--- linux-2.6.12-rc4/include/asm-mips/dma-mapping.h	2005-04-27 13:21:55.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/dma-mapping.h	2005-04-13 19:47:08.655630321 -0500
@@ -5,13 +5,13 @@
 #include <asm/cache.h>
 
 void *dma_alloc_noncoherent(struct device *dev, size_t size,
-			   dma_addr_t *dma_handle, int flag);
+			   dma_addr_t *dma_handle, unsigned int __nocast flag);
 
 void dma_free_noncoherent(struct device *dev, size_t size,
 			 void *vaddr, dma_addr_t dma_handle);
 
 void *dma_alloc_coherent(struct device *dev, size_t size,
-			   dma_addr_t *dma_handle, int flag);
+			   dma_addr_t *dma_handle, unsigned int __nocast flag);
 
 void dma_free_coherent(struct device *dev, size_t size,
 			 void *vaddr, dma_addr_t dma_handle);
diff -urN -x CVS -x .cvsignore linux-2.6.12-rc4/include/asm-mips/elf.h /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/elf.h
--- linux-2.6.12-rc4/include/asm-mips/elf.h	2005-04-27 13:23:30.000000000 -0500
+++ /data/cvs-ext/linux-2.6-mips/linux/include/asm-mips/elf.h	2005-03-21 20:41:42.610238795 -0600
@@ -225,18 +225,17 @@
 #endif /* CONFIG_MIPS64 */
 
 extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
+extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);