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<title>Hardware API Selector: AT91SAM7SE512 Definitions</title>
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<h1>Error Correction Code controller Peripheral</h1>
<null><a name="HECC"></a><b>HECC</b> <i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91S_ECC">AT91S_ECC</a>)</font></i><b> 0xFFFFFFDC </b><i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91C_BASE_HECC">AT91C_BASE_HECC</a>)</font></i>
<br></null><a name="ECC"></a><h2>ECC Software API <i><font size="-1">(<a href="AT91SAM7SE512_h.html#AT91S_ECC">AT91S_ECC</a>)</font></i></h2>
<a name="ECC"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_ECC.html#ECC_CR">ECC_CR</a></font></td><td><font size="-1"> ECC reset register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_ECC.html#ECC_MR">ECC_MR</a></font></td><td><font size="-1"> ECC Page size register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_ECC.html#ECC_SR">ECC_SR</a></font></td><td><font size="-1"> ECC Status register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_ECC.html#ECC_PR">ECC_PR</a></font></td><td><font size="-1"> ECC Parity register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_ECC.html#ECC_NPR">ECC_NPR</a></font></td><td><font size="-1"> ECC Parity N register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91SAM7SE512_ECC.html#ECC_VR">ECC_VR</a></font></td><td><font size="-1"> ECC Version register</font></td></tr>
</null></table><br></null><h2>ECC Register Description</h2>
<null><a name="ECC_CR"></a><h4><a href="#ECC">ECC</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> ECC_CR <i> ECC reset register</i></h4><ul><null><font size="-2"><li><b>HECC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_HECC_CR">AT91C_HECC_CR</a></i> 0xFFFFFFDC</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ECC_RST"></a><b>ECC_RST</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_RST">AT91C_ECC_RST</a></font></td><td><b>ECC reset parity</b><br>0: No Reset. <br> 1: Reset ECC parity + parity N register</td></tr>
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<a name="ECC_MR"></a><h4><a href="#ECC">ECC</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> ECC_MR <i> ECC Page size register</i></h4><ul><null><font size="-2"><li><b>HECC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_HECC_MR">AT91C_HECC_MR</a></i> 0xFFFFFFE0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="ECC_PAGE_SIZE"></a><b>ECC_PAGE_SIZE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_PAGE_SIZE">AT91C_ECC_PAGE_SIZE</a></font></td><td><b>Nand Flash page size</b><br>0: 512 bytes.<br>1: 1024 bytes.<br>2: 2048 bytes.<br>3: 4096 bytes.</td></tr>
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<a name="ECC_SR"></a><h4><a href="#ECC">ECC</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> ECC_SR <i> ECC Status register</i></h4><ul><null><font size="-2"><li><b>HECC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_HECC_SR">AT91C_HECC_SR</a></i> 0xFFFFFFE4</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="ECC_RECERR"></a><b>ECC_RECERR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_RECERR">AT91C_ECC_RECERR</a></font></td><td><b>ECC error</b><br>0: No Error Occured. <br> 1: Single Bit Or Multiple Error Occured</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="ECC_ECCERR"></a><b>ECC_ECCERR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_ECCERR">AT91C_ECC_ECCERR</a></font></td><td><b>ECC single error</b><br>0: No Single Error. <br> 1: Single bit error (correctable) Occured</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="ECC_MULERR"></a><b>ECC_MULERR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_MULERR">AT91C_ECC_MULERR</a></font></td><td><b>ECC_MULERR</b><br>0: No Multiple Errors. <br> 1:Multiple bits error (non-correctable) Occured</td></tr>
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<a name="ECC_PR"></a><h4><a href="#ECC">ECC</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> ECC_PR <i> ECC Parity register</i></h4><ul><null><font size="-2"><li><b>HECC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_HECC_PR">AT91C_HECC_PR</a></i> 0xFFFFFFE8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">3..0</td><td align="CENTER"><a name="ECC_BITADDR"></a><b>ECC_BITADDR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_BITADDR">AT91C_ECC_BITADDR</a></font></td><td><b>Bit address error</b><br>Bit adress Error (position of error for 8-16 bits devices</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..4</td><td align="CENTER"><a name="ECC_WORDADDR"></a><b>ECC_WORDADDR</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_WORDADDR">AT91C_ECC_WORDADDR</a></font></td><td><b>address of the failing bit</b><br>byte-word address of failing bit</td></tr>
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<a name="ECC_NPR"></a><h4><a href="#ECC">ECC</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> ECC_NPR <i> ECC Parity N register</i></h4><ul><null><font size="-2"><li><b>HECC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_HECC_NPR">AT91C_HECC_NPR</a></i> 0xFFFFFFEC</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="ECC_NPARITY"></a><b>ECC_NPARITY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_NPARITY">AT91C_ECC_NPARITY</a></font></td><td><b>ECC parity N </b><br>ECC parity N </td></tr>
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<a name="ECC_VR"></a><h4><a href="#ECC">ECC</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> ECC_VR <i> ECC Version register</i></h4><ul><null><font size="-2"><li><b>HECC</b> <i><a href="AT91SAM7SE512_h.html#AT91C_HECC_VR">AT91C_HECC_VR</a></i> 0xFFFFFFF0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">11..0</td><td align="CENTER"><a name="ECC_VERSION"></a><b>ECC_VERSION</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_VERSION">AT91C_ECC_VERSION</a></font></td><td><b>ECC version number</b><br>ECC version number.Value subject to change. No functionality assiciated. This is the Atmel internal version of the macrocell</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18..16</td><td align="CENTER"><a name="ECC_MFN"></a><b>ECC_MFN</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_ECC_MFN">AT91C_ECC_MFN</a></font></td><td><b>ECC MFN</b><br>ECC MFN Value subject to change. No functionality assiciated</td></tr>
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