at91sam7se512_twi.html

基于AT91SAM7SE512cpu的flash访问例子

<tr><td align="CENTER" bgcolor="#FFFFCC">14 slave</td><td align="CENTER"><a name="TWI_RXBUFF"></a><b>TWI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXBUFF">AT91C_TWI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15 slave</td><td align="CENTER"><a name="TWI_TXBUFE"></a><b>TWI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXBUFE">AT91C_TWI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">0 master</td><td align="CENTER"><a name="TWI_TXCOMP_MASTER"></a><b>TWI_TXCOMP_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXCOMP_MASTER">AT91C_TWI_TXCOMP_MASTER</a></font></td><td><b>Transmission Completed</b><br>0: During the length of the current frame.<br>1: When both holding and shifter registers are empty and STOP condition has been sent or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1 master</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in the TWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2 master</td><td align="CENTER"><a name="TWI_TXRDY_MASTER"></a><b>TWI_TXRDY_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXRDY_MASTER">AT91C_TWI_TXRDY_MASTER</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. <br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6 master</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error (used only in Master and Multi-master mode)</b><br>0: TWI_RHR has not been loaded while RXRDY was set.<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8 master</td><td align="CENTER"><a name="TWI_NACK_MASTER"></a><b>TWI_NACK_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_NACK_MASTER">AT91C_TWI_NACK_MASTER</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12 master</td><td align="CENTER"><a name="TWI_ENDRX"></a><b>TWI_ENDRX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ENDRX">AT91C_TWI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13 master</td><td align="CENTER"><a name="TWI_ENDTX"></a><b>TWI_ENDTX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ENDTX">AT91C_TWI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14 master</td><td align="CENTER"><a name="TWI_RXBUFF"></a><b>TWI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXBUFF">AT91C_TWI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15 master</td><td align="CENTER"><a name="TWI_TXBUFE"></a><b>TWI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXBUFE">AT91C_TWI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9 mult mast</td><td align="CENTER"><a name="TWI_ARBLST_MULTI_MASTER"></a><b>TWI_ARBLST_MULTI_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ARBLST_MULTI_MASTER">AT91C_TWI_ARBLST_MULTI_MASTER</a></font></td><td><b>Arbitration Lost (used only in Multimaster mode)</b><br>0: Arbitration win.<br>1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time.</td></tr>
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<a name="TWI_IDR"></a><h4><a href="#TWI">TWI</a>: <i><a href="AT91SAM7SE512_h.html#AT91_REG">AT91_REG</a></i> TWI_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>TWI</b> <i><a href="AT91SAM7SE512_h.html#AT91C_TWI_IDR">AT91C_TWI_IDR</a></i> 0xFFFB8028</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0 slave</td><td align="CENTER"><a name="TWI_TXCOMP_SLAVE"></a><b>TWI_TXCOMP_SLAVE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXCOMP_SLAVE">AT91C_TWI_TXCOMP_SLAVE</a></font></td><td><b>Transmission Completed</b><br>0: As soon as a Start is detected.<br>1: After a Stop or a Repeated Start + an address different from SADR is detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1 slave</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in the TWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2 slave</td><td align="CENTER"><a name="TWI_TXRDY_SLAVE"></a><b>TWI_TXRDY_SLAVE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXRDY_SLAVE">AT91C_TWI_TXRDY_SLAVE</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: As soon as a data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). <br>1: It indicates that the TWI_THR is empty and that a data has been transmitted and acknowledged.	If TXRDY is high and if a NACK has been detected, it means that the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid loosing it.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3 slave</td><td align="CENTER"><a name="TWI_SVREAD"></a><b>TWI_SVREAD</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SVREAD">AT91C_TWI_SVREAD</a></font></td><td><b>Slave READ (used only in Slave mode)</b><br>When SVACC is low SVREAD is irrelevant. <br>0: Indicates that a write access is performed by a Master.<br>1: Indicates that a read access is performed by a Master.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4 slave</td><td align="CENTER"><a name="TWI_SVACC"></a><b>TWI_SVACC</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SVACC">AT91C_TWI_SVACC</a></font></td><td><b>Slave ACCess (used only in Slave mode)</b><br>0: TWI isn&#146;t addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.<br>1: Indicates that the address decoding sequence has matched. SVACC remains high until a NACK or a STOP condition is detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5 slave</td><td align="CENTER"><a name="TWI_GACC"></a><b>TWI_GACC</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_GACC">AT91C_TWI_GACC</a></font></td><td><b>General Call ACcess (used only in Slave mode)</b><br>0: No General Call has been detected.<br>1: A General Call has been detected.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8 slave</td><td align="CENTER"><a name="TWI_NACK_SLAVE"></a><b>TWI_NACK_SLAVE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_NACK_SLAVE">AT91C_TWI_NACK_SLAVE</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the Master.<br>1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10 slave</td><td align="CENTER"><a name="TWI_SCLWS"></a><b>TWI_SCLWS</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_SCLWS">AT91C_TWI_SCLWS</a></font></td><td><b>Clock Wait State (used only in Slave mode)</b><br>0: The clock isn&#146;t stretched.<br>1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11 slave</td><td align="CENTER"><a name="TWI_EOSACC"></a><b>TWI_EOSACC</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_EOSACC">AT91C_TWI_EOSACC</a></font></td><td><b>End Of Slave ACCess (used only in Slave mode)</b><br>0: A slave access is being performing.<br>1: The Slave Access is finished.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12 slave</td><td align="CENTER"><a name="TWI_ENDRX"></a><b>TWI_ENDRX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ENDRX">AT91C_TWI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13 slave</td><td align="CENTER"><a name="TWI_ENDTX"></a><b>TWI_ENDTX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ENDTX">AT91C_TWI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14 slave</td><td align="CENTER"><a name="TWI_RXBUFF"></a><b>TWI_RXBUFF</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXBUFF">AT91C_TWI_RXBUFF</a></font></td><td><b>RXBUFF Interrupt</b><br>0 = PDC2 Reception Buffer is not full.<br>1 = PDC2 Reception Buffer is full.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15 slave</td><td align="CENTER"><a name="TWI_TXBUFE"></a><b>TWI_TXBUFE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXBUFE">AT91C_TWI_TXBUFE</a></font></td><td><b>TXBUFE Interrupt</b><br>0 = PDC2 Transmission Buffer is not empty.<br>1 = PDC2 Transmission Buffer is empty</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">0 master</td><td align="CENTER"><a name="TWI_TXCOMP_MASTER"></a><b>TWI_TXCOMP_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXCOMP_MASTER">AT91C_TWI_TXCOMP_MASTER</a></font></td><td><b>Transmission Completed</b><br>0: During the length of the current frame.<br>1: When both holding and shifter registers are empty and STOP condition has been sent or when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1 master</td><td align="CENTER"><a name="TWI_RXRDY"></a><b>TWI_RXRDY</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_RXRDY">AT91C_TWI_RXRDY</a></font></td><td><b>Receive holding register ReaDY</b><br>0: No character has been received since the last TWI_RHR read operation.<br>1: A byte has been received in the TWI_RHR since the last read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2 master</td><td align="CENTER"><a name="TWI_TXRDY_MASTER"></a><b>TWI_TXRDY_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_TXRDY_MASTER">AT91C_TWI_TXRDY_MASTER</a></font></td><td><b>Transmit holding register ReaDY</b><br>0: The transmit holding register has not been transferred into shift register. <br>1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6 master</td><td align="CENTER"><a name="TWI_OVRE"></a><b>TWI_OVRE</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_OVRE">AT91C_TWI_OVRE</a></font></td><td><b>Overrun Error (used only in Master and Multi-master mode)</b><br>0: TWI_RHR has not been loaded while RXRDY was set.<br>1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8 master</td><td align="CENTER"><a name="TWI_NACK_MASTER"></a><b>TWI_NACK_MASTER</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_NACK_MASTER">AT91C_TWI_NACK_MASTER</a></font></td><td><b>Not Acknowledged</b><br>0: Each data byte has been correctly received by the far-end side TWI slave component.<br>1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12 master</td><td align="CENTER"><a name="TWI_ENDRX"></a><b>TWI_ENDRX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ENDRX">AT91C_TWI_ENDRX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13 master</td><td align="CENTER"><a name="TWI_ENDTX"></a><b>TWI_ENDTX</b><font size="-2"><br><a href="AT91SAM7SE512_h.html#AT91C_TWI_ENDTX">AT91C_TWI_ENDTX</a></font></td><td><b>End of Receiver Transfer</b><br>0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive.<br>1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active.</td></tr>