📄 rs232.fit.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
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-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
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--A1L72Q is outRegister[0]~reg at LC_X7_Y3_N7
--operation mode is normal
A1L72Q_lut_out = Cpudata[0] & (dataoutset # A1L92Q & sending) # !Cpudata[0] & A1L92Q & sending;
A1L72Q = DFFEAS(A1L72Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L21 is data_to_urst~0 at LC_X8_Y3_N8
--operation mode is normal
A1L21 = sending & A1L72Q;
--A1L92Q is outRegister[1]~reg at LC_X7_Y3_N5
--operation mode is normal
A1L92Q_lut_out = Cpudata[1] & (dataoutset # sending & A1L13Q) # !Cpudata[1] & (sending & A1L13Q);
A1L92Q = DFFEAS(A1L92Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L13Q is outRegister[2]~reg at LC_X7_Y3_N3
--operation mode is normal
A1L13Q_lut_out = A1L33Q & (sending # Cpudata[2] & dataoutset) # !A1L33Q & (Cpudata[2] & dataoutset);
A1L13Q = DFFEAS(A1L13Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L33Q is outRegister[3]~reg at LC_X8_Y3_N2
--operation mode is normal
A1L33Q_lut_out = sending & (A1L53Q # Cpudata[3] & dataoutset) # !sending & (Cpudata[3] & dataoutset);
A1L33Q = DFFEAS(A1L33Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L53Q is outRegister[4]~reg at LC_X8_Y3_N5
--operation mode is normal
A1L53Q_lut_out = sending & (A1L73Q # Cpudata[4] & dataoutset) # !sending & (Cpudata[4] & dataoutset);
A1L53Q = DFFEAS(A1L53Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L73Q is outRegister[5]~reg at LC_X8_Y3_N4
--operation mode is normal
A1L73Q_lut_out = sending & (A1L93Q # Cpudata[5] & dataoutset) # !sending & Cpudata[5] & (dataoutset);
A1L73Q = DFFEAS(A1L73Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L93Q is outRegister[6]~reg at LC_X8_Y3_N9
--operation mode is normal
A1L93Q_lut_out = sending & (A1L14Q # Cpudata[6] & dataoutset) # !sending & (Cpudata[6] & dataoutset);
A1L93Q = DFFEAS(A1L93Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L14Q is outRegister[7]~reg at LC_X8_Y3_N6
--operation mode is normal
A1L14Q_lut_out = Cpudata[7] & (dataoutset);
A1L14Q = DFFEAS(A1L14Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L61Q is dataoutCounter[0]~reg at LC_X7_Y3_N2
--operation mode is normal
A1L61Q_lut_out = !A1L61Q & (sending & !A1L34Q);
A1L61Q = DFFEAS(A1L61Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L81Q is dataoutCounter[1]~reg at LC_X7_Y3_N6
--operation mode is normal
A1L81Q_lut_out = sending & !A1L34Q & (A1L81Q $ A1L61Q);
A1L81Q = DFFEAS(A1L81Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L02Q is dataoutCounter[2]~reg at LC_X7_Y3_N9
--operation mode is normal
A1L02Q_lut_out = sending & !A1L34Q & (A1L02Q $ A1L1);
A1L02Q = DFFEAS(A1L02Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L32Q is dataoutCounter[3]~reg at LC_X7_Y3_N4
--operation mode is normal
A1L32Q_lut_out = A1L22 & (A1L32Q $ (A1L02Q & A1L1));
A1L32Q = DFFEAS(A1L32Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L34Q is SendCountReset~reg at LC_X7_Y3_N1
--operation mode is normal
A1L34Q_lut_out = A1L02Q & !A1L32Q & sending & A1L1;
A1L34Q = DFFEAS(A1L34Q_lut_out, GLOBAL(dataoutclk), VCC, , , , , , );
--A1L22 is dataoutCounter[3]~99 at LC_X7_Y3_N8
--operation mode is normal
A1L22 = sending & !A1L34Q;
--A1L1 is _~50 at LC_X7_Y3_N0
--operation mode is normal
A1L1 = A1L61Q & A1L81Q;
--sending is sending at PIN_31
--operation mode is input
sending = INPUT();
--dataoutset is dataoutset at PIN_49
--operation mode is input
dataoutset = INPUT();
--Cpudata[0] is Cpudata[0] at PIN_27
--operation mode is input
Cpudata[0] = INPUT();
--dataoutclk is dataoutclk at PIN_17
--operation mode is input
dataoutclk = INPUT();
--Cpudata[1] is Cpudata[1] at PIN_40
--operation mode is input
Cpudata[1] = INPUT();
--Cpudata[2] is Cpudata[2] at PIN_38
--operation mode is input
Cpudata[2] = INPUT();
--Cpudata[3] is Cpudata[3] at PIN_53
--operation mode is input
Cpudata[3] = INPUT();
--Cpudata[4] is Cpudata[4] at PIN_54
--operation mode is input
Cpudata[4] = INPUT();
--Cpudata[5] is Cpudata[5] at PIN_47
--operation mode is input
Cpudata[5] = INPUT();
--Cpudata[6] is Cpudata[6] at PIN_52
--operation mode is input
Cpudata[6] = INPUT();
--Cpudata[7] is Cpudata[7] at PIN_132
--operation mode is input
Cpudata[7] = INPUT();
--data_to_urst is data_to_urst at PIN_134
--operation mode is output
data_to_urst = OUTPUT(A1L21);
--outRegister[0] is outRegister[0] at PIN_41
--operation mode is output
outRegister[0] = OUTPUT(A1L72Q);
--outRegister[1] is outRegister[1] at PIN_32
--operation mode is output
outRegister[1] = OUTPUT(A1L92Q);
--outRegister[2] is outRegister[2] at PIN_34
--operation mode is output
outRegister[2] = OUTPUT(A1L13Q);
--outRegister[3] is outRegister[3] at PIN_42
--operation mode is output
outRegister[3] = OUTPUT(A1L33Q);
--outRegister[4] is outRegister[4] at PIN_50
--operation mode is output
outRegister[4] = OUTPUT(A1L53Q);
--outRegister[5] is outRegister[5] at PIN_48
--operation mode is output
outRegister[5] = OUTPUT(A1L73Q);
--outRegister[6] is outRegister[6] at PIN_51
--operation mode is output
outRegister[6] = OUTPUT(A1L93Q);
--outRegister[7] is outRegister[7] at PIN_133
--operation mode is output
outRegister[7] = OUTPUT(A1L14Q);
--dataoutCounter[0] is dataoutCounter[0] at PIN_26
--operation mode is output
dataoutCounter[0] = OUTPUT(A1L61Q);
--dataoutCounter[1] is dataoutCounter[1] at PIN_33
--operation mode is output
dataoutCounter[1] = OUTPUT(A1L81Q);
--dataoutCounter[2] is dataoutCounter[2] at PIN_39
--operation mode is output
dataoutCounter[2] = OUTPUT(A1L02Q);
--dataoutCounter[3] is dataoutCounter[3] at PIN_37
--operation mode is output
dataoutCounter[3] = OUTPUT(A1L32Q);
--SendCountReset is SendCountReset at PIN_28
--operation mode is output
SendCountReset = OUTPUT(A1L34Q);
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