rs232.tan.qmsg

在QuartusII中使用AHDL语言编写一个RS232串行数据通信接口

{ "Info" "ITDB_TH_RESULT" "outRegister\[0\]~reg dataoutset dataoutclk -4.112 ns register " "Info: th for register \"outRegister\[0\]~reg\" (data pin = \"dataoutset\", clock pin = \"dataoutclk\") is -4.112 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dataoutclk destination 2.730 ns + Longest register " "Info: + Longest clock path from clock \"dataoutclk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dataoutclk 1 CLK PIN_17 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutclk } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 8 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns outRegister\[0\]~reg 2 REG LC_X7_Y3_N7 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister\[0\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.261 ns" { dataoutclk outRegister[0]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 17 13 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk outRegister[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 outRegister[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 17 13 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.857 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.857 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns dataoutset 1 PIN PIN_49 8 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_49; Fanout = 8; PIN Node = 'dataoutset'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutset } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 8 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.073 ns) + CELL(0.309 ns) 6.857 ns outRegister\[0\]~reg 2 REG LC_X7_Y3_N7 2 " "Info: 2: + IC(5.073 ns) + CELL(0.309 ns) = 6.857 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister\[0\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "5.382 ns" { dataoutset outRegister[0]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 17 13 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns 26.02 % " "Info: Total cell delay = 1.784 ns ( 26.02 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.073 ns 73.98 % " "Info: Total interconnect delay = 5.073 ns ( 73.98 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "6.857 ns" { dataoutset outRegister[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.857 ns" { dataoutset dataoutset~out0 outRegister[0]~reg } { 0.000ns 0.000ns 5.073ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk outRegister[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 outRegister[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "6.857 ns" { dataoutset outRegister[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.857 ns" { dataoutset dataoutset~out0 outRegister[0]~reg } { 0.000ns 0.000ns 5.073ns } { 0.000ns 1.475ns 0.309ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jan 01 15:58:06 2006 " "Info: Processing ended: Sun Jan 01 15:58:06 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}