rs232.tan.qmsg

在QuartusII中使用AHDL语言编写一个RS232串行数据通信接口

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "dataoutclk register register dataoutCounter\[0\]~reg dataoutCounter\[2\]~reg 275.03 MHz Internal " "Info: Clock \"dataoutclk\" Internal fmax is restricted to 275.03 MHz between source register \"dataoutCounter\[0\]~reg\" and destination register \"dataoutCounter\[2\]~reg\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.903 ns + Longest register register " "Info: + Longest register to register delay is 1.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataoutCounter\[0\]~reg 1 REG LC_X7_Y3_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N2; Fanout = 4; REG Node = 'dataoutCounter\[0\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutCounter[0]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(0.292 ns) 0.870 ns _~50 2 COMB LC_X7_Y3_N0 3 " "Info: 2: + IC(0.578 ns) + CELL(0.292 ns) = 0.870 ns; Loc. = LC_X7_Y3_N0; Fanout = 3; COMB Node = '_~50'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "0.870 ns" { dataoutCounter[0]~reg _~50 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.607 ns) 1.903 ns dataoutCounter\[2\]~reg 3 REG LC_X7_Y3_N9 4 " "Info: 3: + IC(0.426 ns) + CELL(0.607 ns) = 1.903 ns; Loc. = LC_X7_Y3_N9; Fanout = 4; REG Node = 'dataoutCounter\[2\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.033 ns" { _~50 dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.899 ns 47.24 % " "Info: Total cell delay = 0.899 ns ( 47.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.004 ns 52.76 % " "Info: Total interconnect delay = 1.004 ns ( 52.76 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.903 ns" { dataoutCounter[0]~reg _~50 dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.903 ns" { dataoutCounter[0]~reg _~50 dataoutCounter[2]~reg } { 0.000ns 0.578ns 0.426ns } { 0.000ns 0.292ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dataoutclk destination 2.730 ns + Shortest register " "Info: + Shortest clock path from clock \"dataoutclk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dataoutclk 1 CLK PIN_17 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutclk } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 8 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns dataoutCounter\[2\]~reg 2 REG LC_X7_Y3_N9 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N9; Fanout = 4; REG Node = 'dataoutCounter\[2\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.261 ns" { dataoutclk dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[2]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dataoutclk source 2.730 ns - Longest register " "Info: - Longest clock path from clock \"dataoutclk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dataoutclk 1 CLK PIN_17 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutclk } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 8 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns dataoutCounter\[0\]~reg 2 REG LC_X7_Y3_N2 4 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N2; Fanout = 4; REG Node = 'dataoutCounter\[0\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.261 ns" { dataoutclk dataoutCounter[0]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[2]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.903 ns" { dataoutCounter[0]~reg _~50 dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.903 ns" { dataoutCounter[0]~reg _~50 dataoutCounter[2]~reg } { 0.000ns 0.578ns 0.426ns } { 0.000ns 0.292ns 0.607ns } } } { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[2]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutCounter[2]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { dataoutCounter[2]~reg } {  } {  } } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "dataoutCounter\[3\]~reg sending dataoutclk 5.491 ns register " "Info: tsu for register \"dataoutCounter\[3\]~reg\" (data pin = \"sending\", clock pin = \"dataoutclk\") is 5.491 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.184 ns + Longest pin register " "Info: + Longest pin to register delay is 8.184 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sending 1 PIN PIN_31 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 13; PIN Node = 'sending'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { sending } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 14 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.493 ns) + CELL(0.292 ns) 7.254 ns dataoutCounter\[3\]~99 2 COMB LC_X7_Y3_N8 1 " "Info: 2: + IC(5.493 ns) + CELL(0.292 ns) = 7.254 ns; Loc. = LC_X7_Y3_N8; Fanout = 1; COMB Node = 'dataoutCounter\[3\]~99'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "5.785 ns" { sending dataoutCounter[3]~99 } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 12 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.478 ns) 8.184 ns dataoutCounter\[3\]~reg 3 REG LC_X7_Y3_N4 3 " "Info: 3: + IC(0.452 ns) + CELL(0.478 ns) = 8.184 ns; Loc. = LC_X7_Y3_N4; Fanout = 3; REG Node = 'dataoutCounter\[3\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "0.930 ns" { dataoutCounter[3]~99 dataoutCounter[3]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.239 ns 27.36 % " "Info: Total cell delay = 2.239 ns ( 27.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.945 ns 72.64 % " "Info: Total interconnect delay = 5.945 ns ( 72.64 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "8.184 ns" { sending dataoutCounter[3]~99 dataoutCounter[3]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.184 ns" { sending sending~out0 dataoutCounter[3]~99 dataoutCounter[3]~reg } { 0.000ns 0.000ns 5.493ns 0.452ns } { 0.000ns 1.469ns 0.292ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dataoutclk destination 2.730 ns - Shortest register " "Info: - Shortest clock path from clock \"dataoutclk\" to destination register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dataoutclk 1 CLK PIN_17 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutclk } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 8 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns dataoutCounter\[3\]~reg 2 REG LC_X7_Y3_N4 3 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N4; Fanout = 3; REG Node = 'dataoutCounter\[3\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.261 ns" { dataoutclk dataoutCounter[3]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 18 16 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[3]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[3]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "8.184 ns" { sending dataoutCounter[3]~99 dataoutCounter[3]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.184 ns" { sending sending~out0 dataoutCounter[3]~99 dataoutCounter[3]~reg } { 0.000ns 0.000ns 5.493ns 0.452ns } { 0.000ns 1.469ns 0.292ns 0.478ns } } } { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk dataoutCounter[3]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 dataoutCounter[3]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "dataoutclk data_to_urst outRegister\[0\]~reg 8.154 ns register " "Info: tco from clock \"dataoutclk\" to destination pin \"data_to_urst\" through register \"outRegister\[0\]~reg\" is 8.154 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "dataoutclk source 2.730 ns + Longest register " "Info: + Longest clock path from clock \"dataoutclk\" to source register is 2.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dataoutclk 1 CLK PIN_17 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { dataoutclk } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 8 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.711 ns) 2.730 ns outRegister\[0\]~reg 2 REG LC_X7_Y3_N7 2 " "Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister\[0\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "1.261 ns" { dataoutclk outRegister[0]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 17 13 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 79.85 % " "Info: Total cell delay = 2.180 ns ( 79.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.550 ns 20.15 % " "Info: Total interconnect delay = 0.550 ns ( 20.15 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk outRegister[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 outRegister[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 17 13 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.200 ns + Longest register pin " "Info: + Longest register to pin delay is 5.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns outRegister\[0\]~reg 1 REG LC_X7_Y3_N7 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister\[0\]~reg'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { outRegister[0]~reg } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 17 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.761 ns) + CELL(0.114 ns) 0.875 ns data_to_urst~0 2 COMB LC_X8_Y3_N8 1 " "Info: 2: + IC(0.761 ns) + CELL(0.114 ns) = 0.875 ns; Loc. = LC_X8_Y3_N8; Fanout = 1; COMB Node = 'data_to_urst~0'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "0.875 ns" { outRegister[0]~reg data_to_urst~0 } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 34 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.217 ns) + CELL(2.108 ns) 5.200 ns data_to_urst 3 PIN PIN_134 0 " "Info: 3: + IC(2.217 ns) + CELL(2.108 ns) = 5.200 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'data_to_urst'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "4.325 ns" { data_to_urst~0 data_to_urst } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 34 3 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.222 ns 42.73 % " "Info: Total cell delay = 2.222 ns ( 42.73 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.978 ns 57.27 % " "Info: Total interconnect delay = 2.978 ns ( 57.27 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "5.200 ns" { outRegister[0]~reg data_to_urst~0 data_to_urst } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.200 ns" { outRegister[0]~reg data_to_urst~0 data_to_urst } { 0.000ns 0.761ns 2.217ns } { 0.000ns 0.114ns 2.108ns } } }  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "2.730 ns" { dataoutclk outRegister[0]~reg } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.730 ns" { dataoutclk dataoutclk~out0 outRegister[0]~reg } { 0.000ns 0.000ns 0.550ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "5.200 ns" { outRegister[0]~reg data_to_urst~0 data_to_urst } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.200 ns" { outRegister[0]~reg data_to_urst~0 data_to_urst } { 0.000ns 0.761ns 2.217ns } { 0.000ns 0.114ns 2.108ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "sending data_to_urst 11.507 ns Longest " "Info: Longest tpd from source pin \"sending\" to destination pin \"data_to_urst\" is 11.507 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns sending 1 PIN PIN_31 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 13; PIN Node = 'sending'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "" { sending } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 14 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.421 ns) + CELL(0.292 ns) 7.182 ns data_to_urst~0 2 COMB LC_X8_Y3_N8 1 " "Info: 2: + IC(5.421 ns) + CELL(0.292 ns) = 7.182 ns; Loc. = LC_X8_Y3_N8; Fanout = 1; COMB Node = 'data_to_urst~0'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "5.713 ns" { sending data_to_urst~0 } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 34 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.217 ns) + CELL(2.108 ns) 11.507 ns data_to_urst 3 PIN PIN_134 0 " "Info: 3: + IC(2.217 ns) + CELL(2.108 ns) = 11.507 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'data_to_urst'" {  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "4.325 ns" { data_to_urst~0 data_to_urst } "NODE_NAME" } "" } } { "RS232.tdf" "" { Text "D:/altera/quartus50/learn/RS232/RS232.tdf" 34 3 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.869 ns 33.62 % " "Info: Total cell delay = 3.869 ns ( 33.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.638 ns 66.38 % " "Info: Total interconnect delay = 7.638 ns ( 66.38 % )" {  } {  } 0}  } { { "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" "" { Report "D:/altera/quartus50/learn/RS232/db/RS232_cmp.qrpt" Compiler "RS232" "UNKNOWN" "V1" "D:/altera/quartus50/learn/RS232/db/RS232.quartus_db" { Floorplan "D:/altera/quartus50/learn/RS232/" "" "11.507 ns" { sending data_to_urst~0 data_to_urst } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "11.507 ns" { sending sending~out0 data_to_urst~0 data_to_urst } { 0.000ns 0.000ns 5.421ns 2.217ns } { 0.000ns 1.469ns 0.292ns 2.108ns } } }  } 0}