📄 recieve.tdf
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subdesign 'UART'
% ***** Clock frequency is 3.456 MHz ***** %
% ***** Clock period is 289.35 ns ***** %
% ***** Data rate is 28,800 bps ***** %
% ***** DataIn period is 34.72 us ***** %
(
Clock,DataIn :Input;
PosEdge :output;
DataDelay[1..0] :output;
SampleCount[6..0],BitEdge :output;
InRegister[7..0] :output;
SampleCountReset :output;
Receiving,BitCounter[3..0] :Output;
StopReceiving :output;
BitClock :output;
)
Variable
DataDelay[1..0] :DFF;
Receiving :DFF;
InRegister[7..0] :DFF;
SampleCount[6..0] :DFF;
SampleCountReset :DFF;
BitCounter[3..0] :DFF;
BitClock :DFF;
StopReceiving :DFF;
Begin
%***** Connect Clocks *****%
DataDelay[1..0].clk=Clock;
SampleCount[].clk=Clock;
InRegister[].clk=BitClock;
SampleCountReset.clk=Clock;
Receiving.clk=Clock;
StopReceiving.clk=Clock;
BitCounter[].clk=BitClock;
BitClock.clk=BitEdge;
%***** Connect Input Data Line *****%
DataDelay[1].d=DataIn;
InRegister[7].d=DataIn;
InRegister[6..0].d=InRegister[7..1].q;
%***** Perfoorm Edge Detection *****%
DataDelay[0].d=DataDelay[1].q;
PosEdge=DataDelay[1]&!DataDelay[0];
%***** Set the Reciving Signle *****%
Receiving.d=PosEdge#Receiving.q&!StopReceiving;
%***** Generate BitEdge Pulse *****%
if(Receiving)then
SampleCount[].d=(SampleCount[].q+1)&!SampleCountReset;
Case SampleCount[] is
WHEN H"3C" =>
BitEdge=Vcc;
SampleCountReset.d=Vcc;
WHEN OTHERS =>
BitEdge=Gnd;
SampleCountReset.d=Gnd;
End Case;
end if;
%***** Centers and edges *****%
BitClock.d=!BitClock.q;
BitClock.clrn=Receiving;
%***** Increment Bit Counter *****%
BitCounter[].d=BitCounter[]+1;
BitCounter[].clrn=Receiving;
%***** Set end of data word *****%
if (BItCounter[]==H"9") Then
StopReceiving.d=Vcc;
else
StopReceiving.d=Gnd;
end if;
End;
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