📄 rs232.tan.rpt
字号:
; N/A ; None ; 4.164 ns ; dataoutset ; outRegister[2]~reg ; dataoutclk ;
+-------+--------------+------------+------------+-----------------------+------------+
+--------------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-----------------------+-------------------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-----------------------+-------------------+------------+
; N/A ; None ; 8.154 ns ; outRegister[0]~reg ; data_to_urst ; dataoutclk ;
; N/A ; None ; 7.381 ns ; outRegister[7]~reg ; outRegister[7] ; dataoutclk ;
; N/A ; None ; 7.223 ns ; dataoutCounter[1]~reg ; dataoutCounter[1] ; dataoutclk ;
; N/A ; None ; 7.214 ns ; outRegister[2]~reg ; outRegister[2] ; dataoutclk ;
; N/A ; None ; 7.165 ns ; dataoutCounter[0]~reg ; dataoutCounter[0] ; dataoutclk ;
; N/A ; None ; 7.163 ns ; SendCountReset~reg ; SendCountReset ; dataoutclk ;
; N/A ; None ; 7.074 ns ; dataoutCounter[3]~reg ; dataoutCounter[3] ; dataoutclk ;
; N/A ; None ; 6.849 ns ; outRegister[1]~reg ; outRegister[1] ; dataoutclk ;
; N/A ; None ; 6.798 ns ; dataoutCounter[2]~reg ; dataoutCounter[2] ; dataoutclk ;
; N/A ; None ; 6.791 ns ; outRegister[3]~reg ; outRegister[3] ; dataoutclk ;
; N/A ; None ; 6.787 ns ; outRegister[0]~reg ; outRegister[0] ; dataoutclk ;
; N/A ; None ; 6.777 ns ; outRegister[6]~reg ; outRegister[6] ; dataoutclk ;
; N/A ; None ; 6.463 ns ; outRegister[4]~reg ; outRegister[4] ; dataoutclk ;
; N/A ; None ; 6.461 ns ; outRegister[5]~reg ; outRegister[5] ; dataoutclk ;
+-------+--------------+------------+-----------------------+-------------------+------------+
+----------------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+---------+--------------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+---------+--------------+
; N/A ; None ; 11.507 ns ; sending ; data_to_urst ;
+-------+-------------------+-----------------+---------+--------------+
+-------------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------------+-----------------------+------------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------------+-----------------------+------------+
; N/A ; None ; -4.112 ns ; dataoutset ; outRegister[0]~reg ; dataoutclk ;
; N/A ; None ; -4.112 ns ; dataoutset ; outRegister[2]~reg ; dataoutclk ;
; N/A ; None ; -4.164 ns ; dataoutset ; outRegister[3]~reg ; dataoutclk ;
; N/A ; None ; -4.166 ns ; dataoutset ; outRegister[7]~reg ; dataoutclk ;
; N/A ; None ; -4.167 ns ; dataoutset ; outRegister[4]~reg ; dataoutclk ;
; N/A ; None ; -4.167 ns ; dataoutset ; outRegister[5]~reg ; dataoutclk ;
; N/A ; None ; -4.168 ns ; dataoutset ; outRegister[6]~reg ; dataoutclk ;
; N/A ; None ; -4.388 ns ; Cpudata[5] ; outRegister[5]~reg ; dataoutclk ;
; N/A ; None ; -4.398 ns ; dataoutset ; outRegister[1]~reg ; dataoutclk ;
; N/A ; None ; -4.558 ns ; Cpudata[6] ; outRegister[6]~reg ; dataoutclk ;
; N/A ; None ; -4.595 ns ; Cpudata[3] ; outRegister[3]~reg ; dataoutclk ;
; N/A ; None ; -4.617 ns ; Cpudata[4] ; outRegister[4]~reg ; dataoutclk ;
; N/A ; None ; -4.690 ns ; sending ; outRegister[1]~reg ; dataoutclk ;
; N/A ; None ; -4.692 ns ; sending ; outRegister[0]~reg ; dataoutclk ;
; N/A ; None ; -4.698 ns ; sending ; dataoutCounter[2]~reg ; dataoutclk ;
; N/A ; None ; -4.700 ns ; sending ; dataoutCounter[0]~reg ; dataoutclk ;
; N/A ; None ; -4.701 ns ; sending ; SendCountReset~reg ; dataoutclk ;
; N/A ; None ; -4.777 ns ; sending ; dataoutCounter[1]~reg ; dataoutclk ;
; N/A ; None ; -4.786 ns ; sending ; outRegister[2]~reg ; dataoutclk ;
; N/A ; None ; -4.805 ns ; Cpudata[1] ; outRegister[1]~reg ; dataoutclk ;
; N/A ; None ; -4.861 ns ; sending ; outRegister[4]~reg ; dataoutclk ;
; N/A ; None ; -4.868 ns ; sending ; outRegister[5]~reg ; dataoutclk ;
; N/A ; None ; -4.869 ns ; sending ; outRegister[6]~reg ; dataoutclk ;
; N/A ; None ; -4.870 ns ; sending ; outRegister[3]~reg ; dataoutclk ;
; N/A ; None ; -4.999 ns ; Cpudata[2] ; outRegister[2]~reg ; dataoutclk ;
; N/A ; None ; -5.189 ns ; Cpudata[0] ; outRegister[0]~reg ; dataoutclk ;
; N/A ; None ; -5.358 ns ; Cpudata[7] ; outRegister[7]~reg ; dataoutclk ;
; N/A ; None ; -5.439 ns ; sending ; dataoutCounter[3]~reg ; dataoutclk ;
+---------------+-------------+-----------+------------+-----------------------+------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Sun Jan 01 15:58:06 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off RS232 -c RS232 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "dataoutclk" is an undefined clock
Info: Clock "dataoutclk" Internal fmax is restricted to 275.03 MHz between source register "dataoutCounter[0]~reg" and destination register "dataoutCounter[2]~reg"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.903 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N2; Fanout = 4; REG Node = 'dataoutCounter[0]~reg'
Info: 2: + IC(0.578 ns) + CELL(0.292 ns) = 0.870 ns; Loc. = LC_X7_Y3_N0; Fanout = 3; COMB Node = '_~50'
Info: 3: + IC(0.426 ns) + CELL(0.607 ns) = 1.903 ns; Loc. = LC_X7_Y3_N9; Fanout = 4; REG Node = 'dataoutCounter[2]~reg'
Info: Total cell delay = 0.899 ns ( 47.24 % )
Info: Total interconnect delay = 1.004 ns ( 52.76 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "dataoutclk" to destination register is 2.730 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'
Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N9; Fanout = 4; REG Node = 'dataoutCounter[2]~reg'
Info: Total cell delay = 2.180 ns ( 79.85 % )
Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: - Longest clock path from clock "dataoutclk" to source register is 2.730 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'
Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N2; Fanout = 4; REG Node = 'dataoutCounter[0]~reg'
Info: Total cell delay = 2.180 ns ( 79.85 % )
Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "dataoutCounter[3]~reg" (data pin = "sending", clock pin = "dataoutclk") is 5.491 ns
Info: + Longest pin to register delay is 8.184 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 13; PIN Node = 'sending'
Info: 2: + IC(5.493 ns) + CELL(0.292 ns) = 7.254 ns; Loc. = LC_X7_Y3_N8; Fanout = 1; COMB Node = 'dataoutCounter[3]~99'
Info: 3: + IC(0.452 ns) + CELL(0.478 ns) = 8.184 ns; Loc. = LC_X7_Y3_N4; Fanout = 3; REG Node = 'dataoutCounter[3]~reg'
Info: Total cell delay = 2.239 ns ( 27.36 % )
Info: Total interconnect delay = 5.945 ns ( 72.64 % )
Info: + Micro setup delay of destination is 0.037 ns
Info: - Shortest clock path from clock "dataoutclk" to destination register is 2.730 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'
Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N4; Fanout = 3; REG Node = 'dataoutCounter[3]~reg'
Info: Total cell delay = 2.180 ns ( 79.85 % )
Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: tco from clock "dataoutclk" to destination pin "data_to_urst" through register "outRegister[0]~reg" is 8.154 ns
Info: + Longest clock path from clock "dataoutclk" to source register is 2.730 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'
Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister[0]~reg'
Info: Total cell delay = 2.180 ns ( 79.85 % )
Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Longest register to pin delay is 5.200 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister[0]~reg'
Info: 2: + IC(0.761 ns) + CELL(0.114 ns) = 0.875 ns; Loc. = LC_X8_Y3_N8; Fanout = 1; COMB Node = 'data_to_urst~0'
Info: 3: + IC(2.217 ns) + CELL(2.108 ns) = 5.200 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'data_to_urst'
Info: Total cell delay = 2.222 ns ( 42.73 % )
Info: Total interconnect delay = 2.978 ns ( 57.27 % )
Info: Longest tpd from source pin "sending" to destination pin "data_to_urst" is 11.507 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_31; Fanout = 13; PIN Node = 'sending'
Info: 2: + IC(5.421 ns) + CELL(0.292 ns) = 7.182 ns; Loc. = LC_X8_Y3_N8; Fanout = 1; COMB Node = 'data_to_urst~0'
Info: 3: + IC(2.217 ns) + CELL(2.108 ns) = 11.507 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'data_to_urst'
Info: Total cell delay = 3.869 ns ( 33.62 % )
Info: Total interconnect delay = 7.638 ns ( 66.38 % )
Info: th for register "outRegister[0]~reg" (data pin = "dataoutset", clock pin = "dataoutclk") is -4.112 ns
Info: + Longest clock path from clock "dataoutclk" to destination register is 2.730 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 13; CLK Node = 'dataoutclk'
Info: 2: + IC(0.550 ns) + CELL(0.711 ns) = 2.730 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister[0]~reg'
Info: Total cell delay = 2.180 ns ( 79.85 % )
Info: Total interconnect delay = 0.550 ns ( 20.15 % )
Info: + Micro hold delay of destination is 0.015 ns
Info: - Shortest pin to register delay is 6.857 ns
Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_49; Fanout = 8; PIN Node = 'dataoutset'
Info: 2: + IC(5.073 ns) + CELL(0.309 ns) = 6.857 ns; Loc. = LC_X7_Y3_N7; Fanout = 2; REG Node = 'outRegister[0]~reg'
Info: Total cell delay = 1.784 ns ( 26.02 % )
Info: Total interconnect delay = 5.073 ns ( 73.98 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
Info: Processing ended: Sun Jan 01 15:58:06 2006
Info: Elapsed time: 00:00:01
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