rs232.tdf

在QuartusII中使用AHDL语言编写一个RS232串行数据通信接口

% ***** Clock frequency is 3.456 MHz ***** %
% ***** Clock period is 289.35 ns ***** %
% ***** Data rate is 14,400 bps ***** %
% ***** Dataout period is 69.44 us ***** %
subdesign RS232
(
	%clock          				%
	dataoutset,dataoutclk					:input;
	data_to_urst					:output;
	Cpudata[7..0]				:input;
	outRegister[8..0]           :output;
	dataoutCounter[3..0]		:output;
	SendCountReset				:output;
	sending						:input;
	
	Clock               :Input;
	PosEdge                    :output;
	DataDelay[1..0]            :output;
	SampleCount[7..0],BitEdge  :output;
	InRegister[7..0]           :output;
	SampleCountReset           :output;
	Receiving,BitCounter[3..0] :Output;
	StopReceiving              :output;
	BitClock                   :output;
)
Variable
	% for sending message%
	outRegister[8..0]           :dff;
	dataoutCounter[3..0]		:dff;
	SendCountReset				:dff;
	%for recieving message%
	DataDelay[1..0]           :DFF;
	Receiving                 :DFF;
	InRegister[7..0]          :DFF;
	SampleCount[7..0]         :DFF;
	SampleCountReset          :DFF;
	BitCounter[3..0]          :DFF;
	BitClock                  :DFF;
	StopReceiving             :DFF;
begin
	%set clock%
	outRegister[8..0].clk=dataoutclk;
	dataoutCounter[3..0].clk=dataoutclk;
	SendCountReset.clk=dataoutclk;
	%clock for recieving%	
	DataDelay[1..0].clk=Clock;
	SampleCount[].clk=Clock;
	InRegister[].clk=BitClock;
	SampleCountReset.clk=Clock;
	Receiving.clk=Clock;
	StopReceiving.clk=Clock;
	BitCounter[].clk=BitClock;
	BitClock.clk=BitEdge;
	
	% send data to recieve machine%          		
	if (sending==1) then 	
		if (dataoutset==1) then
			outRegister[8..1].d=Cpudata[7..0];
			outRegister[0].d=vcc;
		else outRegister[7..0].d=outRegister[8..1].q;
			outRegister[8].d=gnd;
		end if;
			
			if outRegister[]>0 then
				dataoutCounter[3..0].d=(dataoutCounter[3..0].q+1)&!SendCountReset;
				Case dataoutCounter[] is
                    WHEN H"8" =>
                        SendCountReset.d=Vcc;
                    WHEN OTHERS =>
                        SendCountReset.d=Gnd;
     			End Case;
			else dataoutCounter[3..0].d=0;
			end if;
		
		data_to_urst=outRegister[0].q;
	
	end if;	
	
	%******* for recieving ************%
	%***** Connect Input Data Line *****%
	DataDelay[1].d=data_to_urst;
	InRegister[7].d=data_to_urst;
	InRegister[6..0].d=InRegister[7..1].q;

	%***** Perfoorm Edge Detection *****%
	DataDelay[0].d=DataDelay[1].q;
	PosEdge=DataDelay[1]&!DataDelay[0];
	
	%***** Set the Reciving Signle *****%
	Receiving.d=PosEdge#Receiving.q&!StopReceiving;

	%***** Generate BitEdge Pulse *****%
	if(Receiving)then
       SampleCount[].d=(SampleCount[].q+1)&!SampleCountReset;
             Case SampleCount[] is
                    WHEN H"78" =>
                        BitEdge=Vcc;
                        SampleCountReset.d=Vcc;
                    WHEN OTHERS =>
                         BitEdge=Gnd;
                        SampleCountReset.d=Gnd;
             End Case;
	end if;
	
	%***** Centers and edges *****%
	BitClock.d=!BitClock.q;
	BitClock.clrn=Receiving;

	%***** Increment Bit Counter *****%
	BitCounter[].d=BitCounter[]+1;
	BitCounter[].clrn=Receiving;

	%***** Set end of data word *****%
	if (BItCounter[]==H"9") Then
        StopReceiving.d=Vcc;
	else
        StopReceiving.d=Gnd;
	end if;    
	end;