e100.h

linux intel 网卡驱动,利用他可以让inel的pro 100 网卡进行网络配置和实用

/*******************************************************************************

  
  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  
  This program is free software; you can redistribute it and/or modify it 
  under the terms of the GNU General Public License as published by the Free 
  Software Foundation; either version 2 of the License, or (at your option) 
  any later version.
  
  This program is distributed in the hope that it will be useful, but WITHOUT 
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
  more details.
  
  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc., 59 
  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  
  The full GNU General Public License is included in this distribution in the
  file called LICENSE.
  
  Contact Information:
  Linux NICS <[e-mail]>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/

#ifndef _E100_INC_
#define _E100_INC_

#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/version.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <linux/reboot.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <asm/processor.h>
#ifdef SIOCETHTOOL
#include <linux/ethtool.h>
#include <linux/inetdevice.h>
#endif

#ifdef IANS
#include "ans_driver.h"
#endif

#ifdef E100_IDIAG_PRO_SUPPORT
#include "idiag_pro.h"
#include "idiag_e100.h"
#endif /*E100_IDIAG_PRO_SUPPORT */

#include <linux/if.h>
#include <asm/uaccess.h>
#include <linux/proc_fs.h>
#include <linux/ip.h>

#define E100_RX_CONGESTION_CONTROL
#include "e100_kcompat.h"

#ifdef	ETHTOOL_GREGS
#define E100_REGS_LEN 1
#endif
/*
 *  Configure parameters for buffers per controller.
 *  If the machine this is being used on is a faster machine (i.e. > 150MHz)
 *  and running on a 10MBS network then more queueing of data occurs. This
 *  may indicate the some of the numbers below should be adjusted.  Here are
 *  some typical numbers:
 *                             MAX_TCB 64
 *                             MAX_RFD 64
 *  The default numbers give work well on most systems tests so no real
 *  adjustments really need to take place.  Also, if the machine is connected
 *  to a 100MBS network the numbers described above can be lowered from the
 *  defaults as considerably less data will be queued.
 */

#define TX_FRAME_CNT   8	/* consecutive transmit frames per interrupt */
/* TX_FRAME_CNT must be less than MAX_TCB    */

#define E100_DEFAULT_TCB   64
#define E100_MIN_TCB       2*TX_FRAME_CNT + 3	/* make room for at least 2 interrupts */
#define E100_MAX_TCB       1024

#define E100_DEFAULT_RFD   64
#define E100_MIN_RFD       8
#define E100_MAX_RFD       1024

#define E100_DEFAULT_XSUM         true
#define E100_DEFAULT_BER          ZLOCK_MAX_ERRORS
#define E100_DEFAULT_SPEED_DUPLEX 0
#define E100_DEFAULT_FC           0
#define E100_DEFAULT_IFS          true
#define E100_DEFAULT_UCODE        true

#define TX_THRSHLD     8

/* IFS parameters */
#define MIN_NUMBER_OF_TRANSMITS_100 1000
#define MIN_NUMBER_OF_TRANSMITS_10  100

#define E100_MAX_NIC 16

#define E100_MAX_SCB_WAIT	100	/* Max udelays in wait_scb */
#define E100_MAX_CU_IDLE_WAIT	50	/* Max udelays in wait_cus_idle */

/* HWI feature related constant */
#define HWI_MAX_LOOP                    100
#define MAX_SAME_RESULTS		3
#define HWI_REGISTER_GRANULARITY        80	/* register granularity = 80 Cm */
#define HWI_NEAR_END_BOUNDARY           1000	/* Near end is defined as < 10 meters */

/* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled.
 * In some situations, such as the TCP windowing algorithm, it may be
 * better to limit the growth of the bundle size than let it go as
 * high as it can, because that could cause too much added latency.
 * The default is six, because this is the number of packets in the
 * default TCP window size.  A value of 1 would make CPUSaver indicate
 * an interrupt for every frame received.  If you do not want to put
 * a limit on the bundle size, set this value to xFFFF.
 */
#define E100_DEFAULT_CPUSAVER_BUNDLE_MAX	6
#define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY	0x600
#define E100_DEFAULT_BUNDLE_SMALL_FR		false
#ifdef E100_RX_CONGESTION_CONTROL
#define E100_DEFAULT_RX_CONGESTION_CONTROL	true
#endif

/* end of configurables */

/* ====================================================================== */
/*                                hw                                      */
/* ====================================================================== */

/* timeout for command completion */
#define E100_CMD_WAIT   100	/* iterations */

struct driver_stats {
	struct net_device_stats net_stats;

	unsigned long tx_late_col;
	unsigned long tx_ok_defrd;
	unsigned long tx_one_retry;
	unsigned long tx_mt_one_retry;
	unsigned long rcv_cdt_frames;
	unsigned long xmt_fc_pkts;
	unsigned long rcv_fc_pkts;
	unsigned long rcv_fc_unsupported;
	unsigned long xmt_tco_pkts;
	unsigned long rcv_tco_pkts;
	unsigned long rx_intr_pkts;
#ifdef E100_RX_CONGESTION_CONTROL
	unsigned long rx_tasklet_pkts;
	unsigned long poll_intr_switch;
#endif
};

/* TODO: kill me when we can do C99 */
#define false		(0)
#define true		(1)

/* Changed for 82558 and 82559 enhancements */
/* defines for 82558/9 flow control CSR values */
#define DFLT_FC_THLD       0x00	/* Rx FIFO threshold of 0.5KB free  */
#define DFLT_FC_CMD        0x00	/* FC Command in CSR */

/* ====================================================================== */
/*                              equates                                   */
/* ====================================================================== */

/*
 * These are general purpose defines 
 */

/* Bit Mask definitions */
#define BIT_0       0x0001
#define BIT_1       0x0002
#define BIT_2       0x0004
#define BIT_3       0x0008
#define BIT_4       0x0010
#define BIT_5       0x0020
#define BIT_6       0x0040
#define BIT_7       0x0080
#define BIT_8       0x0100
#define BIT_9       0x0200
#define BIT_10      0x0400
#define BIT_11      0x0800
#define BIT_12      0x1000
#define BIT_13      0x2000
#define BIT_14      0x4000
#define BIT_15      0x8000
#define BIT_28      0x10000000

#define BIT_0_2     0x0007
#define BIT_0_3     0x000F
#define BIT_0_4     0x001F
#define BIT_0_5     0x003F
#define BIT_0_6     0x007F
#define BIT_0_7     0x00FF
#define BIT_0_8     0x01FF
#define BIT_0_13    0x3FFF
#define BIT_0_15    0xFFFF
#define BIT_1_2     0x0006
#define BIT_1_3     0x000E
#define BIT_2_5     0x003C
#define BIT_3_4     0x0018
#define BIT_4_5     0x0030
#define BIT_4_6     0x0070
#define BIT_4_7     0x00F0
#define BIT_5_7     0x00E0
#define BIT_5_12    0x1FE0
#define BIT_5_15    0xFFE0
#define BIT_6_7     0x00c0
#define BIT_7_11    0x0F80
#define BIT_8_10    0x0700
#define BIT_9_13    0x3E00
#define BIT_12_15   0xF000
#define BIT_8_15    0xFF00

#define BIT_16_20   0x001F0000
#define BIT_21_25   0x03E00000
#define BIT_26_27   0x0C000000

/* Transmit Threshold related constants */
#define DEFAULT_TX_PER_UNDERRUN         20000

#define MAX_MULTICAST_ADDRS             64
#define MAX_FILTER                      16

#define FULL_DUPLEX      2
#define HALF_DUPLEX      1

/*
 * These defines are specific to the 82557 
 */

/* E100 PORT functions -- lower 4 bits */
#define PORT_SOFTWARE_RESET         0
#define PORT_SELFTEST               1
#define PORT_SELECTIVE_RESET        2
#define PORT_DUMP                   3

/* SCB Status Word bit definitions */
/* Interrupt status/ack fields */
/* ER and FCP interrupts for 82558 masks  */
#define SCB_STATUS_ACK_MASK        BIT_8_15	/* Status Mask */
#define SCB_STATUS_ACK_CX          BIT_15	/* CU Completed Action Cmd */
#define SCB_STATUS_ACK_FR          BIT_14	/* RU Received A Frame */
#define SCB_STATUS_ACK_CNA         BIT_13	/* CU Became Inactive (IDLE) */
#define SCB_STATUS_ACK_RNR         BIT_12	/* RU Became Not Ready */
#define SCB_STATUS_ACK_MDI         BIT_11	/* MDI read or write done */
#define SCB_STATUS_ACK_SWI         BIT_10	/* S/W generated interrupt */
#define SCB_STATUS_ACK_ER          BIT_9	/* Early Receive */
#define SCB_STATUS_ACK_FCP         BIT_8	/* Flow Control Pause */

/*- CUS Fields */
#define SCB_CUS_MASK            (BIT_6 | BIT_7)	/* CUS 2-bit Mask */
#define SCB_CUS_IDLE            0	/* CU Idle */
#define SCB_CUS_SUSPEND         BIT_6	/* CU Suspended */
#define SCB_CUS_ACTIVE          BIT_7	/* CU Active */

/*- RUS Fields */
#define SCB_RUS_IDLE            0	/* RU Idle */
#define SCB_RUS_MASK            BIT_2_5	/* RUS 3-bit Mask */
#define SCB_RUS_SUSPEND         BIT_2	/* RU Suspended */
#define SCB_RUS_NO_RESOURCES    BIT_3	/* RU Out Of Resources */
#define SCB_RUS_READY           BIT_4	/* RU Ready */
#define SCB_RUS_SUSP_NO_RBDS    (BIT_2 | BIT_5)	/* RU No More RBDs */
#define SCB_RUS_NO_RBDS         (BIT_3 | BIT_5)	/* RU No More RBDs */
#define SCB_RUS_READY_NO_RBDS   (BIT_4 | BIT_5)	/* RU Ready, No RBDs */

/* SCB Command Word bit definitions */
/*- CUC fields */
/* Changing mask to 4 bits */
#define SCB_CUC_MASK            BIT_4_7	/* CUC 4-bit Mask */
#define SCB_CUC_NOOP            0
#define SCB_CUC_START           BIT_4	/* CU Start */
#define SCB_CUC_RESUME          BIT_5	/* CU Resume */
/* Changed for 82558 enhancements */
#define SCB_CUC_STATIC_RESUME   (BIT_5 | BIT_7)	/* 82558/9 Static Resume */
#define SCB_CUC_DUMP_ADDR       BIT_6	/* CU Dump Counters Address */
#define SCB_CUC_DUMP_STAT       (BIT_4 | BIT_6)	/* CU Dump stat. counters */
#define SCB_CUC_LOAD_BASE       (BIT_5 | BIT_6)	/* Load the CU base */
/* Below was defined as BIT_4_7 */
#define SCB_CUC_DUMP_RST_STAT   BIT_4_6	/* CU Dump & reset statistics cntrs */

/*- RUC fields */
#define SCB_RUC_MASK            BIT_0_2	/* RUC 3-bit Mask */
#define SCB_RUC_START           BIT_0	/* RU Start */
#define SCB_RUC_RESUME          BIT_1	/* RU Resume */
#define SCB_RUC_ABORT           BIT_2	/* RU Abort */
#define SCB_RUC_LOAD_HDS        (BIT_0 | BIT_2)	/* Load RFD Header Data Size */
#define SCB_RUC_LOAD_BASE       (BIT_1 | BIT_2)	/* Load the RU base */
#define SCB_RUC_RBD_RESUME      BIT_0_2	/* RBD resume */

/* Interrupt fields (assuming byte addressing) */
#define SCB_INT_MASK            BIT_0	/* Mask interrupts */
#define SCB_SOFT_INT            BIT_1	/* Generate a S/W interrupt */
/*  Specific Interrupt Mask Bits (upper byte of SCB Command word) */
#define SCB_FCP_INT_MASK        BIT_2	/* Flow Control Pause */
#define SCB_ER_INT_MASK         BIT_3	/* Early Receive */
#define SCB_RNR_INT_MASK        BIT_4	/* RU Not Ready */
#define SCB_CNA_INT_MASK        BIT_5	/* CU Not Active */
#define SCB_FR_INT_MASK         BIT_6	/* Frame Received */
#define SCB_CX_INT_MASK         BIT_7	/* CU eXecution w/ I-bit done */
#define SCB_BACHELOR_INT_MASK   BIT_2_7	/* 82558 interrupt mask bits */

#define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7

/* EEPROM bit definitions */
/*- EEPROM control register bits */
#define EN_TRNF          0x10	/* Enable turnoff */
#define EEDO             0x08	/* EEPROM data out */
#define EEDI             0x04	/* EEPROM data in (set for writing data) */
#define EECS             0x02	/* EEPROM chip select (1=hi, 0=lo) */
#define EESK             0x01	/* EEPROM shift clock (1=hi, 0=lo) */

/*- EEPROM opcodes */
#define EEPROM_READ_OPCODE          06
#define EEPROM_WRITE_OPCODE         05
#define EEPROM_ERASE_OPCODE         07
#define EEPROM_EWEN_OPCODE          19	/* Erase/write enable */
#define EEPROM_EWDS_OPCODE          16	/* Erase/write disable */

/*- EEPROM data locations */
#define EEPROM_NODE_ADDRESS_BYTE_0      0
#define EEPROM_COMPATIBILITY_WORD       3
#define EEPROM_PWA_NO                   8
#define EEPROM_ID_WORD			0x0A

#define EEPROM_SUM                      0xbaba

// Zero Locking Algorithm definitions:
#define ZLOCK_ZERO_MASK		0x00F0
#define ZLOCK_MAX_READS		50	
#define ZLOCK_SET_ZERO		0x2010
#define ZLOCK_MAX_SLEEP		300 * HZ	
#define ZLOCK_MAX_ERRORS	300

/* E100 Action Commands */
#define CB_IA_ADDRESS           1
#define CB_CONFIGURE            2
#define CB_MULTICAST            3
#define CB_TRANSMIT             4
#define CB_LOAD_MICROCODE       5
#define CB_LOAD_FILTER		8
#define CB_MAX_NONTX_CMD        9
#define CB_IPCB_TRANSMIT        9

/* Pre-defined Filter Bits */
#define CB_FILTER_EL            0x80000000
#define CB_FILTER_FIX           0x40000000
#define CB_FILTER_ARP           0x08000000
#define CB_FILTER_IA_MATCH      0x02000000

/* Command Block (CB) Field Definitions */
/*- CB Command Word */
#define CB_EL_BIT           BIT_15	/* CB EL Bit */
#define CB_S_BIT            BIT_14	/* CB Suspend Bit */
#define CB_I_BIT            BIT_13	/* CB Interrupt Bit */
#define CB_TX_SF_BIT        BIT_3	/* TX CB Flexible Mode */
#define CB_CMD_MASK         BIT_0_3	/* CB 4-bit CMD Mask */
#define CB_CID_DEFAULT      (0x1f << 8)	/* CB 5-bit CID (max value) */

/*- CB Status Word */