📄 c6xdspinit.c
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//C6xdskinit.c Init DSP,AD,McBSP
void comm_intr()
{
/*************************************************************************/
/* CONFIG EMIFA REGISTER */
/*************************************************************************/
*(unsigned volatile int *)EMIFA_GCTL=0x5203C;//0001273c; // her and me 0101 0010 0000 0011 1100
/*CLK4EN(4),CLK6EN(3),EK1EN(5),EK2EN(16) IS SET '1' OTHERS IS SET '0' */
/* EK2RATE(19 18) IS SET "10" ECLKOUT2 RUNS AT 1/4*EMIF INPUT CLOCK */
/*(2,8,9,10) bit is read only '1' */
// ECLKOUT1=1/6 CPU CYCLE
//*****GCTL管DSP时钟输出的**********//
//*(unsigned volatile int *)EMIFA_CE0=0x21924631; //P363
*(unsigned volatile int *)EMIFA_CE0=0x00004030;//ffffff3f ; //P363
/*WRITE SETUP(31-28): 0010 */
/*WRITE STROBE(27-22): 000110 */
/*WRITE HOLD(21-20): 01 */
/*READ SETUP(19-16): 0010 */
/*TURN-AROUND TIME(15-14): 01 */
/*READ STROBE(13-8): 0110 */
/*MTYPE(4-7): 0011 DEFINE THE RAM TYPE IS 32-BIT SDRAM;*/
/*WRITE HOLD WIDTH MSB(3): 0 */
/*READ HOLD(2-0): 001 */
*(unsigned volatile int *)EMIFA_SDRAMEXT=0x004b508;//001b4d09;//p362 0 0101 0100 0101 0000 1011
/*TCL(0) 0 :INDICATE CAS LATENCY IS 2 CYCLES in sdram data sheeet*/
/*TRAS(3-1) 100 :INDICATE THE tras cycles is 5 */
/*TRRD(4) 0 :INDICATE THE trrd cycles is 2 ???? */
/*TWR(6-5) 00 :INDICATE THE twr cycles is 1 ???? */
/*THZP(8-7) 10 :INDICATE THE thzp cycles is 3 ???? */
/*RD2RD(9) 0 :P362 advise */
/*RD2DEAC(11-10) 01 : P362 advise */
/*RD2WR(14-12) 011 : P362 advise */
/*R2WDQM(16-15) 01 : P362 advise */
/*WR2WR(17) 0 : P362 advise */
/*WR2DEAC(19-18) 01 : P362 advise */
/*WR2RD (20) 0 : P362 advise */
*(unsigned volatile int *)EMIFA_SDRAMCTL =0x57116000 ;//1000111000100010101000000000000
/*SDBSZ(30) 1 :INDICATE TWO BANK ADDRESS BITS ARE USED(4 BANK)
recorrding to sdram structor */
/*SDRSZ(29-28) 01 :INDICATE 12 ROW ADDRESS BITS ARE USED */
/*SDCSZ(27-26) 01 :INDICATE 08 COLUMN ADDRESS BITS ARE USED */
/*RFEN(25) 1 :INDICATE THE SDRAM REFRESH IS ENABLED */
/*INIT(24) 1 :FORCE THE SDRAM INITIALIZATION */
/*TRCD(23-20) 0001 :INDICATE THE trcd is 2 CYCLES
in sdram data sheet */
/*TRP(19-16) 0001 :INDICATE THE trp is 2 CYCLES */
/*TRC(15-12) 0110 :INDICATE THE trc is 7 CYCLES */
/*RSV(11-1) 0 :THIS IS RESERVED */
/*SLFRFR(0) 0 :INDICATE THE SELF_REFRESH MODE IS NOT ENABLE */
*(unsigned volatile int *)EMIFA_SDRAMREF =0x00005DC ;//600; //1500,15us
/*PERIOD(11-0) :INDICATE THE REFRESH PERIOD IS tref/tcyc .tref=64ms/4266*/
/*************************************************************************/
/* CONFIG EMIFB REGISTER */
/*************************************************************************/
*(unsigned volatile int *)EMIFB_GCTL =0x5203c;
/*CLK4EN(4),CLK6EN(3),EK1EN(5),EK2EN(16) IS SET '1' OTHERS IS SET '0' */
/* EK2RATE(19 18) IS SET "10" ECLKOUT2 RUNS AT 1/4*EMIF INPUT CLOCK */
/*(2,8,9,10) bit is read only '1' */
*(unsigned volatile int *)EMIFB_CE0 =0x1071C811 ; //P374 advised
/*WRITE SETUP(31-28): 0001 */
/*WRITE STROBE(27-22): 000001 */
/*WRITE HOLD(21-20): 11 */
/*READ SETUP(19-16): 0001 */
/*TURN-AROUND TIME(15-14): 11 */
/*READ STROBE(13-8): 001000 */
/*MTYPE(4-7): 0001//define the ram type is 16 bit interface */
/*WRITE HOLD WIDTH MSB(3): 0 */
/*READ HOLD(2-0): 001 */
*(unsigned volatile int *)EMIFB_CE0SECCTL=0x00000021 ; //P367//it is useless for asfifo
/*RESERVED(31-7)*/
/*SNCCLK(6): 0 Select Synchronization clock as ECLKOUT1*/
/*RENEN(5): 0 ADS mode. question!!!!!!*/
/*CEEXT(4): 0 CE goes inactive after the final command has been issued*/
/*SYNCWL(3-2):10 Synchronous interface data write latency 2 cycles*/
/*SYNCRL(1-0):01 Synchronous interface data read latency 1 cycle*/
/*************************************************************************/
/* CONFIG EMIFB REGISTER FOR FALSH */
/*************************************************************************/
//*(unsigned volatile int *)EMIFB_CE1 =0x2231d000 ; //10 0010 0011 0001 1101 0000 0000 0000
*(unsigned volatile int *)EMIFB_CE1 =0x2231ce08 ;
//*(unsigned volatile int *)EMIFB_CE1 =0x8422C403 ; //P374 advised
/*WRITE SETUP(31-28): 0010 */
/*WRITE STROBE(27-22): 001000 */
/*WRITE HOLD(21-20): 11 */
/*READ SETUP(19-16): 0001 */
/*TURN-AROUND TIME(15-14): 11 */
/*READ STROBE(13-8): 010000/001110 */
/*MTYPE(4-7): 0000 async8 */
/*WRITE HOLD WIDTH MSB(3): 0/1 */
/*READ HOLD(2-0): 000 */
*(unsigned volatile int *)EMIFB_CE1SECCTL=0x00000021 ; //P367//it is useless for asfifo
/*RESERVED(31-7)*/
/*SNCCLK(6): 0 Select Synchronization clock as ECLKOUT1*/
/*RENEN(5): 0 ADS mode. question!!!!!!*/
/*CEEXT(4): 0 CE goes inactive after the final command has been issued*/
/*SYNCWL(3-2):10 Synchronous interface data write latency 2 cycles*/
/*SYNCRL(1-0):01 Synchronous interface data read latency 1 cycle*/
/*************************************************************************/
/* CONFIG EDMA REGISTER */
/*************************************************************************/
// EDMA24 FOR TRANSMIT
*(unsigned volatile int *)(EVENT24_PARAMS+OPT)=0x510f6003;
/*PRI(31-29): 010 Medium priority EDMA transfer*/
/*ESIZE(28-27):10 8-bit halfword//01--16bits*/
/*2DS(26): 0 1-dimensional destination source*/
/*SUM(25-24): 01 Source address increment depends on the 2DS and FS bits*/
/*2DD(23): 0 1-dimensional destination*/
/*DUM(22-21): 00 Fixed address mode. No destination address modification*/
/*TCINT(20): 0 Transfer complete indication is disabled*/
/*TCC(19-16): 1111 TCC works in conjunction with the TCCM bits to provide
a 6-bit transfer complete code*/
/*Reserved(15):0 */
/*TCCM(14-13): 11 Transfer complete code most-significant bits(Value)*/
/*ATCINT(12): 0 Alternate transfer complete indication is disabled*/
/*Reserved(11):0 */
/*ATCC(10-5): 000 000 Alternate transfer complete code bits. This 6-bit value is used
to set the bit in the EDMA channel interrupt pending register*/
/*Reserved(4): 0 */
/*PDTS(3): 0 Peripheral device transfer (PDT) mode for read is enabled*/
/*PDTD(2): 0 Peripheral device transfer (PDT) mode for write is enabled*/
/*LINK(1): 1 Linking of event parameters is enabled*/
/*FS(0): 1 Channel is frame synchronized*/
*(unsigned volatile int *)(EVENT24_PARAMS+SRC)=0x00025000;
*(unsigned volatile int *)(EVENT24_PARAMS+CNT)=0x00000114;
*(unsigned volatile int *)(EVENT24_PARAMS+DST)=0x60000008;
*(unsigned volatile int *)(EVENT24_PARAMS+IDX)=0x00000000;
*(unsigned volatile int *)(EVENT24_PARAMS+LNK)=0x00000600;
*(unsigned volatile int *)(EVENT24L_PARAMS+OPT)=0x510f6003;
*(unsigned volatile int *)(EVENT24L_PARAMS+SRC)=0x00025000;
*(unsigned volatile int *)(EVENT24L_PARAMS+CNT)=0x00000114;
*(unsigned volatile int *)(EVENT24L_PARAMS+DST)=0x60000008;
*(unsigned volatile int *)(EVENT24L_PARAMS+IDX)=0x00000000;
*(unsigned volatile int *)(EVENT24L_PARAMS+LNK)=0x00000600;
*(unsigned volatile int *)PQSR=0xffffffff;
*(unsigned volatile int *)CIPR=0x00000000;
*(unsigned volatile int *)CIER=0x00000000;
*(unsigned volatile int *)CCER=0x00000000;
*(unsigned volatile int *)EER =0x00000000;
*(unsigned volatile int *)ECR =0x00000000;
*(unsigned volatile int *)ESR =0x00000000;
/* configure timer*/
*(unsigned volatile int *)TIMER0_CTRL=0x00000215;
//bit 31~12 :0 reserved;
//bit 11 :0 read only;
//bit 10 :0 uninverted TINP drives timer;
//bit 9 :1 timer clock source cpu clock/8;
//bit 8 :0 tout pulse time;
//bit 7 :0 counter is disable and held in current state;
//bit 6 :0 no effect in timer;
//bit 5 :0 reserved;
//bit 4 :1 tout time period 2;
//bit 3 :0 don't care;
//bit 2 :1 timer output;
//bit 1 :0 uninverted time out;
//bit 0 :1 timer output pin;
*(unsigned volatile int *)TIMER0_COUNT=0x0;
*(unsigned volatile int *)TIMER0_PRD=0x3c;
//timer period is 12.5MHz;
}
void McBSP_initial()
{ /* configure DSP2 McBSP1 */
*(unsigned volatile int *)McBSP1_SPCR=0x0;
//bit 31~26 :0 reserved;
//bit 25,24 :01 when emulator is halted,the mcbsp is halted;
//bit 23 :1 frame synchron is generated;
//bit 22 :1 sample generator is working;
//bit 21,20 :00 xint is drived by copy;
//bit 19 :0 synchronization error isn't detected;
//bit 18 :0 read only;
//bit 17 :0 read only;
//bit 16 :0 transmit port is disable; !!!!!!!
//bit 15 :0 digitial loop mode is disable;
//bit 14,13 :01 right-justed and sign-extended in msb;
//bit 12,11 :01 clock stop mode is disable; !!!!!!!
//bit 10~8 :000reserved;
//bit 7 :1 dx is enabled;
//bit 6 :0 reserved;
//bit 5,4 :00 don't care;
//bit 3 :1 don't care;
//bit 2 :0 read only;
//bit 1 :0 read only;
//bit 0 :0 receiver port is disable; !!!!!!!!
*(unsigned volatile int *)McBSP1_SRGR=0x2010001e;
//bit 31 :0 sample generator is free running;
//bit 30 :0 don't care;
//bit 29 :1 sample-rate generator is drived from cpu;
//bit 28 :1 transmit frame is from cpu;
//bit 27~16 :0x010 frame period is 16+1;
//bit 15~8 :0x00 frame pulse is 0+1;
//bit 7~0 :0x1e divered-down numbers;
*(unsigned volatile int *)McBSP1_XCR=0x00000040;
//bit 31~18 :0 single_phase frame;
//bit 17,16 :01 1 bit delay;
//bit 14~8 :0x1 1 word in a phase;
//bit 7~5 :010 word length is 16 bit;
//bit 4~0 :0 don't care;
*(unsigned volatile int *)McBSP1_PCR=0x00000a0b;
//bit 31~12 :0x00000 ;multiplex pin setted as series pins
//bit 11 :1 frame out is drived internals;
//bit 10 :0 frame in is drived externals;
//bit 9 :1 mcbsp is master;
//bit 8 :0 don't care;
//bit 7 :0 reserved;
//bit 6 :0 don't care;
//bit 5 :0 don't care;
//bit 4 :0 don't care;
//bit 3 :0 transmit frame active low;
//bit 2 :0 don't care;
//bit 1 :1 don't care;
//bit 0 :1 don't care;
*(unsigned volatile int *)McBSP1_SPCR=0x01c33880;
}
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