class.ptf

SDRAM Controller For Altera SOPC Builder and NIOS on DE2 kit board

CLASS altera_up_avalon_sdram
{
   ASSOCIATED_FILES
   {
      Add_Program  = "default";
      Edit_Program = "default";
      Bind_Program = "bind";
      # Generator_Libraries = "../../bin/europa";
      Generator_Program = "up_sdram.pl";
      Test_Generator_Program = "up_sodimm.pl";
   }

   MODULE_DEFAULTS
   {
      class         = "altera_up_avalon_sdram";
      class_version = "6.0";
      Default_Module_Name = "sdram";
      iss_model_name = "altera_memory";

      SLAVE s1
      {
         SYSTEM_BUILDER_INFO
         {
            Bus_Type                      = "avalon";
            Address_Alignment             = "dynamic";
            Has_IRQ                       = "0";
            Maximum_Pending_Read_Transactions = "5";
            Read_Wait_States              = "peripheral_controlled";
            Write_Wait_States             = "peripheral_controlled";
            Is_Memory_Device              = "1";
            Address_Width                 = "12";
            Data_Width                    = "16";
            Simulation_Num_Lanes          = "1";
         }
         PORT_WIRING
         {
            # These are the top level ports.
            # Avalon ports will be added during system generation.
            PORT zs_addr
            {
               direction = "output";
               width = "12";
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "16";
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "4";
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
            }
         }
      }
      SYSTEM_BUILDER_INFO
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled                   = "1";
         Default_Module_Name          = "sdram";
         Disable_Simulation_Port_Wiring = "0";
         Top_Level_Ports_Are_Enumerated = "1";
      }
      WIZARD_SCRIPT_ARGUMENTS
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "16";
         sdram_addr_width = "12";
         sdram_row_width = "12";
         sdram_col_width = "8";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "15.625";
         powerup_delay = "100";
         cas_latency = "3";
         t_rfc = "70";
         t_rp = "20";
         t_mrd = "3";
         t_rcd = "20";
         t_ac = "5.5";
         t_wr = "14";
         init_refresh_commands = "2";
         init_nop_delay = "0";
         shared_data = "0";
         starvation_indicator = "0";
         tristate_bridge_slave = "";
         is_initialized   = "0";
		 sdram_bank_width = "2";
      }
      SIMULATION
      {
         Fix_Me_Up = "";
         DISPLAY
         {
# These signals are "of interest" and are added to the waveform window, etc.
# The name of the section (e.g. "a2" or "f") doesn't "mean" anything, except
# that the signals will be displayed in the waveform window in-order, as
# sorted by these otherwise-meaningless names.
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "0";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "0";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "0";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "1";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "1";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "1";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "1";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "1";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "1";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "1";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "1";
            }
         }
      }
   }
   USER_INTERFACE
   {
      USER_LABELS
      {
         name="SDRAM";
         description="SDRAM Controller for DE2 and DE1 Board";
         technology="University Program DE1 Board,University Program DE2 Board";
      }
      LINKS
      {
         LINK help
         {
            title="Data Sheet";
			url = "../doc/SDRAM_Controller.pdf";
         }
      }
      WIZARD_UI default
      {
			title = "SRAM - {{ $MOD }}";
			$$address_width = "{{ $WSA/sdram_addr_width + 4; }}";
	        $$num_bankbits = "{{ log2($WSA/sdram_num_banks); }}";

			#CONTEXT 
			#{
			#	H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
			#	M = "";
			#	SBI_global_signals		= "SYSTEM_BUILDER_INFO";
			#	# SBI_avalon_sram_slave	= "SLAVE avalon_sram_slave/SYSTEM_BUILDER_INFO";
			#}
            CONTEXT
            {
               WSA="WIZARD_SCRIPT_ARGUMENTS";
               S_SBI="SLAVE s1/SYSTEM_BUILDER_INFO";
               SBI="SYSTEM_BUILDER_INFO";
               # simulation display signals_section
               SDS="SIMULATION/DISPLAY";
               CONTENTS="WIZARD_SCRIPT_ARGUMENTS/CONTENTS srec";
            }
			GROUP
			{
				layout = "vertical";
				TEXT 
				{
					title = "SDRAM Controller";
				}
				TEXT 
				{
					title = "DE1 and DE2 Development and Education Boards";
				}
				TEXT 
				{
					title = "Total memory:  8 MBytes";
				}
				TEXT 
				{
					title = "Memory Format: 4M x 16Bit words";
				}
			}
			ACTION wizard_finish
			{
			   $WSA/is_initialized = "{{ ($CONTENTS/Kind != 'blank') }}";
			   $MOD/SYSTEM_BUILDER_INFO/View/Settings_Summary = 
			      "{{ $$cmsib_width; }} x {{ $$width; }}<br>
			       {{ $$mem_size_in_MBytes_str; }}<br>
			       {{ $$mem_size_in_MBits_str; }}
			       {{ if ($WSA/shared_data) 
			          '<br>Sharing Pins Via Tristate Bridge'; }}";
			   $SBI/Disable_Simulation_Port_Wiring = "{{ $WSA/shared_data; }}";
			   $S_SBI/Maximum_Pending_Read_Transactions = 
			      "{{ 3 + ($WSA/cas_latency) + $WSA/register_data_in +
			          ( 2 * $WSA/shared_data ); }}";
			   $S_SBI/Address_Width = "{{ $$address_width; }}";
			   $WSA/sdram_bank_width = "{{ $$num_bankbits; }}";
			   $SDS/SIGNAL k/suppress = 
			      "{{ ! ($WSA/shared_data && $WSA/starvation_indicator); }}";
			   $SDS/SIGNAL m/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL n/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL o/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL p/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL q/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL r/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL s/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL t/suppress = "{{ $WSA/shared_data; }}";
			   $SDS/SIGNAL u/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL v/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL w/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL x/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL y/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z0/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z1/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z2/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z3/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z4/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z5/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z6/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z7/suppress = "{{ ! $WSA/shared_data; }}";
			   $SDS/SIGNAL z8/suppress = "{{ ! $WSA/shared_data; }}";


			   #
			   # SLAVE s1 settings
			   #
			   
			   # set any SLAVE s1 variable port widths
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_addr/width = "{{ $WSA/sdram_addr_width }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_ba/width   = "{{ $WSA/sdram_bank_width }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_cs_n/width = "{{ $WSA/sdram_num_chipselects }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_dq/width   = "{{ $WSA/sdram_data_width }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_dqm/width  = "{{ $WSA/sdram_data_width / 8 }}";
			   
			   # only enable the SLAVE s1 ports if NOT in tristate mode
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_addr/Is_Enabled  = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_ba/Is_Enabled    = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_cas_n/Is_Enabled = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_cke/Is_Enabled   = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_cs_n/Is_Enabled  = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_dq/Is_Enabled    = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_dqm/Is_Enabled   = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_ras_n/Is_Enabled = "{{ ! $WSA/shared_data; }}";
			   $MOD/SLAVE s1/PORT_WIRING/PORT zs_we_n/Is_Enabled  = "{{ ! $WSA/shared_data; }}";
			   
			}
      }
      WIZARD_UI bind
      {
         CONTEXT
         {
            MOD = "";
            WSA = "WIZARD_SCRIPT_ARGUMENTS";
            S_SBI="SLAVE s1/SYSTEM_BUILDER_INFO";
         }
         visible = "{{ $WSA/shared_data; }}";
         align = "left";
         GROUP
         {
            title = "SDRAM Controller / Tristate Bridge Binding";
            align = "left";
            spacing = "5";
            TABLE
            {
               glue = "0";
               java = "sopc_builder.sopc_slave_table";
               COLUMN name
               {
                  title = "SDRAM";
                  width = "200";
                  type = "text";
                  editable = "0";
               }
               COLUMN slave
               {
                  title = "Select Tristate Bridge";
                  width = "200";
                  type = "combo";
                  contents = "slave";
               }
               ROW
               {
                  COLUMN name
                  {
                     title = "Tristate Bridge Selection";
                  }
                  COLUMN slave
                  {
                     data = "$WSA/tristate_bridge_slave";
                     filter = "altera_avalon_tri_state_bridge";
                     emancipated = "1";
                     required = "{{ $WSA/shared_data; }} ";
                  }
               }
            }
            TEXT
            {
               title = "Note: This can only be changed if Tri-state Sharing mode is selected in the 'SDRAM Controller' Wizard.";
               glue = "0";
            }
            # SPR 158980: validation to ensure that when SDRAM shares a TSB that it's on the same clock
            error = "{{  if ($WSA/shared_data != 0 && sopc_get_clock_source($WSA/tristate_bridge_slave) !=  sopc_get_clock_source($MOD))
                         '<b>'+$MOD+'</b>: SDRAM sharing pins with '+$WSA/tristate_bridge_slave+' must share same clock.';   }}";
         }
      }
   }
}