fft.tdf

VHDL 函数信号发生器 VHDL 函数信号发生器

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity chabiao2 is
port(adress:in integer;
sel:in std_logic_vector(1 downto 0);
data:out integer);
end chabiao2;

architecture a of chabiao2 is
begin
process(adress,sel)
begin
if sel="00" then
case adress is
when 0=>data<=0;
when 10=>data<=17;
when 20=>data<=34;
when 30=>data<=50;
when 40=>data<=64;
when 50=>data<=76;
when 60=>data<=86;
when 70=>data<=94;
when 80=>data<=98;
when 90=>data<=100;
when 100=>data<=98;
when 110=>data<=94;
when 120=>data<=86;
when 130=>data<=76;
when 140=>data<=64;
when 150=>data<=50;
when 160=>data<=34;
when 170=>data<=17;
when 180=>data<=0;
when 190=>data<=17;
when 200=>data<=34;
when 210=>data<=50;
when 220=>data<=64;
when 230=>data<=76;
when 240=>data<=86;
when 250=>data<=94;
when 260=>data<=98;
when 270=>data<=100;
when 280=>data<=98;
when 290=>data<=94;
when 300=>data<=86;
when 310=>data<=76;
when 320=>data<=64;
when 330=>data<=50;
when 340=>data<=34;
when 350=>data<=17;
when 359=>data<=0;
when others=>null;
end case;
elsif sel="01"then
 if adress<180 then
   data<=255;
  else data<=0;
 end if;
elsif sel="10"then
 data<=adress/2;
else
  if adress<180 then
   data<=adress;
else
   data<=360- adress;
  end if;
end if;
end process;
end a;