controler.vdh

VHDL 函数信号发生器 VHDL 函数信号发生器

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity controler is
port(clk:in std_logic;
datain :in std_logic;
ad:out std_logic_vector(15 downto 0);
frep:out std_logic_vector(15 downto 0));
end controler;

architecture dataflow of controler is
signal out1:std_logic_vector(15 downto 0);
begin

process(clk,datain)
variable temp:std_logic_vector(15 downto 0);
begin
if clk'event and clk='1'then
temp:=temp(15 downto 0)&datain;
end if;
out<=temp;
end process;

process(out1(15))
begin
if(out1(15)='1')then
ad<=out1(15 downto 0);   
else
frep<=out1(15 downto 0);
end if;
end process;

end dataflow;