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📄 dsp.h

📁 ZORAN 962/966 SOURCE CODE,DVD chip
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/**********************************************************************************
 *  Copyright (c) 2001 ZORAN Corporation, All Rights Reserved
 *  THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF ZORAN CORPORATION
 *
 *  File: "dsp.h"
 *
 * Description:
 * ============
 * Definitions for DSP<->CPU interface
 * 
 * Log:
 * ====
 * $Revision: $
 * Last Modified by $Author: $ at $Modtime: $ 
 **********************************************************************************
 * Updates:
 **********************************************************************************
 * $Log: $
 * 
 * 
 *********************************************************************************/
#include "Config.h"		/* Global Configuration - do not remove! */


#ifndef DSP_H
#define DSP_H


/*** Include Files ***************************************************************/
#include "Include\cpu_address.h"
#include "Drive\Zfe\zfe.h"


/*** Defines *********************************************************************/
#define CPU2DSP_FIFO_SIZE			30
#define DSP2CPU_FIFO_SIZE			30
#define CPU2DSP_NUM_OF_MSG			42
#define DSP2CPU_NUM_OF_MSG			33


/*** Typedefs ********************************************************************/
typedef enum
{
	DSP_EXIT_FREEZE					= 0x0,
	DSP_FREEZE						= 0x1,
	DSP_FREEZE_MASK					= 0x1,

	DSP_EXIT_RESET					= 0x0,
	DSP_RESET						= 0x2,
	DSP_RESET_MASK					= 0x2,

	DSP_NMI							= 0x4,
	DSP_INT1						= 0x8,
} DSP_CONTROL_BITS;


typedef enum
{
	CPU2DSP_FIFO_READ				= 0x5a0,
	CPU2DSP_FIFO_WRITE				= 0x5a1,
	CPU2DSP_FIFO_START				= 0x5a2,
	DSP2CPU_FIFO_READ				= 0x5c0,
	DSP2CPU_FIFO_WRITE				= 0x5c1,
	DSP2CPU_FIFO_START				= 0x5c2,
	DSP_SHARE_MEM_BASE				= 0x5e0
} DSP_ADDRESSES;


typedef enum
{
	DSP_SERVO_STATUS				= DSP_SHARE_MEM_BASE + 0x00,
	DSP_SERVO_ERROR_STATUS			= DSP_SHARE_MEM_BASE + 0x01,
	DSP_DEFECT_INDICATION			= DSP_SHARE_MEM_BASE + 0x04,
	DSP_RF_DAC_OFFSET_SHADOW		= DSP_SHARE_MEM_BASE + 0x05,
	DSP_ECCENTRISITY				= DSP_SHARE_MEM_BASE + 0x06,
	DSP_SERVO_TR_GAIN_L0_SHADOW		= DSP_SHARE_MEM_BASE + 0x07,
	DSP_SERVO_TR_GAIN_L1_SHADOW		= DSP_SHARE_MEM_BASE + 0x08,
	DSP_RF_GAIN_SHADOW				= DSP_SHARE_MEM_BASE + 0x09,
	DSP_RF_MIN_MAX_SHADOW			= DSP_SHARE_MEM_BASE + 0x0a,
	DSP_SERVO_TILT					= DSP_SHARE_MEM_BASE + 0x0b,
	DSP_SERVO_MAX_DEFECT_LENGTH		= DSP_SHARE_MEM_BASE + 0x0f,
	DSP_SERVO_FE_OFFSET_SHADOW		= DSP_SHARE_MEM_BASE + 0x10,
	DSP_SERVO_JITTER_MEASURE		= DSP_SHARE_MEM_BASE + 0x11,
	DSP_SERVO_WAVE_FORM				= DSP_SHARE_MEM_BASE + 0x12,
	DSP_SERVO_DRC_THRESHOLD			= DSP_SHARE_MEM_BASE + 0x13,
	DSP_SERVO_NBCA_ROTATION_TIME	= DSP_SHARE_MEM_BASE + 0x14,
#ifdef DRV_ENHANCED_MEDIA_DETECTION
	DSP_SERVO_MEDIA_DETECTION_TIME 	= DSP_SHARE_MEM_BASE + 0x16,
#endif
#ifdef CD_USE_DPD
	DSP_SERVO_TE_MAG				= DSP_SHARE_MEM_BASE + 0x17,
#endif
#ifdef FTA_SUPPORT
    DSP_FTA_CPU_BUFFER_IDX1         = DSP_SHARE_MEM_BASE + 0x00,
	DSP_FTA_CPU_BUFFER_IDX2         = DSP_SHARE_MEM_BASE + 0x01,
	DSP_FTA_CPU_BUFFER_IDX3         = DSP_SHARE_MEM_BASE + 0x02,
	DSP_FTA_CPU_BUFFER_IDX4         = DSP_SHARE_MEM_BASE + 0x03,
	DSP_FTA_CPU_BUFFER_IDX5         = DSP_SHARE_MEM_BASE + 0x04,
	DSP_FTA_DSP_BUFFER_IDX1         = DSP_SHARE_MEM_BASE + 0x05,
	DSP_FTA_DSP_BUFFER_IDX2         = DSP_SHARE_MEM_BASE + 0x06,
	DSP_FTA_DSP_BUFFER_IDX3         = DSP_SHARE_MEM_BASE + 0x07,
	DSP_FTA_DSP_BUFFER_IDX4         = DSP_SHARE_MEM_BASE + 0x08,
	DSP_FTA_DSP_BUFFER_IDX5         = DSP_SHARE_MEM_BASE + 0x09,
#endif
} DSP_SHARED_MEM_ADDRESSES;


typedef enum
{
	CPU_DSP_NOP						= 0x0000,
	CPU_DSP_RE_FOCUS				= 0x0001,
	CPU_DSP_SW_VER					= 0x0002,
	CPU_DSP_POKE					= 0x0003,
	CPU_DSP_PEEK					= 0x0004,
	CPU_DSP_CPOKE					= 0x0005,
	CPU_DSP_CPEEK					= 0x0006,
	CPU_DSP_SET_SPEED				= 0x0007,
	CPU_DSP_SPIN_UP					= 0x0008,
	CPU_DSP_SPIN_DOWN				= 0x0009,
	CPU_DSP_HOME					= 0x000a,
	CPU_DSP_SLED_LEAP				= 0x000b,
	CPU_DSP_DETECT_MEDIA			= 0x000c,
	CPU_DSP_JUMP					= 0x000d,
	CPU_DSP_FAR_JUMP				= 0x000e,
	CPU_DSP_KEEP_HEAD				= 0x000f,
	CPU_DSP_PLAY					= 0x0010,
	CPU_DSP_LASER_OFF				= 0x0011,
	CPU_DSP_SET_LAYER_0				= 0x0012,
	CPU_DSP_SET_LAYER_1				= 0x0013,
	CPU_DSP_START_CALIBRATION		= 0x0014,
	CPU_DSP_SET_PARAM				= 0x0015,
    CPU_DSP_GET_PARAM				= 0x0016,
	CPU_DSP_POWER_DOWN				= 0x0017,
	CPU_DSP_START_CALIB_PHASE		= 0x0018,
	CPU_DSP_GO_TO_STATE				= 0x0019,
	CPU_DSP_GET_MEDIA_TYPE		    = 0x001A,
	CPU_DSP_START_JITTER_METER		= 0x001B,
	CPU_DSP_START_FE_CALIB			= 0x001C,
	CPU_DSP_LASER_ON				= 0x001D,
	CPU_DSP_SET_MEDIA_TYPE		    = 0x001E,
	CPU_DSP_MOTOR_DRIVER_MUTE		= 0x001F,
	CPU_DSP_MOTOR_DRIVER_UNMUTE		= 0x0020,
	CPU_DSP_JUMP_REPORT				= 0x0021,
	CPU_DSP_DMA_COMPLETE			= 0x0022,
	CPU_DSP_STOP_JITTER_METER		= 0x0023,
	CPU_DSP_START_NBCA_SEARCH		= 0x0024,
	CPU_DSP_CONFIRM_MEDIA_TYPE		= 0x0025,
	CPU_DSP_START_DDX_SAMPLING		= 0x0026,
	CPU_DSP_DO_LCD_DC_DC_CALIB		= 0x0026,
	CPU_DSP_FTA_PLAY                = 0x0027,
	CPU_DSP_FTA_STOP                = 0x0028,
	CPU_DSP_FTA_ADD_PID             = 0x0029
} CPU_DSP_CMD;


typedef enum
{
	DSP_CPU_NOP						= (int)0x8000,
	DSP_CPU_INIT_DONE				= (int)0x8001,
	DSP_CPU_SW_VER_RES				= (int)0x8002,
	DSP_CPU_SERVO_ERROR				= (int)0x8003,
	DSP_CPU_PEEK_RES				= (int)0x8004,
	DSP_CPU_CPEEK_RES				= (int)0x8005,
	DSP_CPU_SPIN_UP_DONE			= (int)0x8006,
	DSP_CPU_SPIN_DOWN_DONE			= (int)0x8007,
	DSP_CPU_LEAP_COMP				= (int)0x8008,
	DSP_CPU_MEDIA_TYPE_RES			= (int)0x8009,
	DSP_CPU_JUMP_COMP				= (int)0x800a,
	DSP_CPU_PLAYING					= (int)0x800b,
	DSP_CPU_LASER_IS_OFF			= (int)0x800c,
	DSP_CPU_SET_LAYER_DONE			= (int)0x800d,
	DSP_CPU_UART_WRITE				= (int)0x800e,
	DSP_CPU_GET_PARAM_RES			= (int)0x800f,
	DSP_CPU_POWER_DOWN_DONE			= (int)0x8010,
	DSP_CPU_CALIB_PHASE_COMP		= (int)0x8011,
	DSP_CPU_GET_JITTER_RES			= (int)0x8012,
	DSP_CPU_FE_CALIB_COMP			= (int)0x8013,
	DSP_CPU_LASER_ON_DONE		    = (int)0x8014,
	DSP_CPU_JUMP_STARTED			= (int)0x8015,
	DSP_CPU_DMA_START				= (int)0x8016,
	DSP_CPU_DMA_ABORT				= (int)0x8017,
	DSP_CPU_NBCA_FOUND				= (int)0x8018,
	DSP_CPU_SAVE_SERVO_PARAM		= (int)0x8019,
	DSP_CPU_CHANGE_TO_DVD			= (int)0x801a,
	DSP_CPU_CHANGE_TO_CD			= (int)0x801b,
	DSP_CPU_FINISH_DDX_SAMPLING		= (int)0x801c,
	DSP_CPU_LCD_DC_DC_CALIB_DONE	= (int)0x801c,
	DSP_CPU_FTA_PLAY_STARTED        = (int)0x801d,
	DSP_CPU_FTA_STOP_DONE           = (int)0x801e,
	DSP_CPU_FTA_ADD_PID_DONE        = (int)0x801f,
	DSP_CPU_FTA_SECTION_READY		= (int)0x8020,
#ifdef DEBUG_DSP
	DSP_CPU_ANY_MSG					= (int)0x8100,
	DSP_CPU_NO_MSG					= (int)0x8101,
#endif
	DSP_CPU_SERVO_REQ_ERROR			= (int)0x8105
} DSP_CPU_CMD;


/*** Extern **********************************************************************/


/*** Public Functions ************************************************************/
ZFE_ERR_CODE DSP_ReadMsg(DSP_CPU_CMD * op_code, int max_params, UINT16 * params);
ZFE_ERR_CODE DSP_WriteMsg(CPU_DSP_CMD op_code, int num_params, UINT16 * params);
void __interrupt DSP_Isr(void);
#ifdef BG_PRINT
void		 DSP_SendParamsToBGPrint(UINT16 * params);
#endif
UINT16		 DSP_DramRead(UINT16 addr);
void		 DSP_DramWrite(UINT16 addr, UINT16 data);


#endif

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