📄 usbohci.h
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/* usbohci.h - OpenHCI Specification 1.0 header */
/* Copyright 2004 TAEBAEK Soft Corp. */
/*
modification history
--------------------
02e,28nov05,jmLee version control sync.
02d,01aug05,jmLee support transfer large block(above 64K).
02c,25jul05,jmLee version control sync.
01b,18jul05,jmLee increase ED & TD, insufficient when connect thumb drive using hub.
01a,26jul04,jmLee created.
*/
#ifndef __INCusbohcih
#define __INCusbohcih
#ifdef __cplusplus
extern "C" {
#endif
/* OHCI 1.0 Specifications */
/* The Control and Status Partition */
#define HC_RR 0x00000000 /* HC Revision Register */
#define HC_CR 0x00000004 /* HC Control Register */
#define HC_CSR 0x00000008 /* HC Command Status Register */
#define HC_ISR 0x0000000C /* HC Interrupt Status Register */
#define HC_IER 0x00000010 /* HC Interrupt Enable Register */
#define HC_IDR 0x00000014 /* HC Interrupt Disable Register */
/* Memory Pointer Partition */
#define HC_HCCAR 0x00000018 /* HC Host Controller Communication Area Register */
#define HC_PCEDR 0x0000001C /* HC Period Current ED Register */
#define HC_CHEDR 0x00000020 /* HC Control Head ED Register */
#define HC_CCEDR 0x00000024 /* HC Control Current ED Register */
#define HC_BHEDR 0x00000028 /* HC Bulk Head ED Register */
#define HC_BCEDR 0x0000002C /* HC Bulk Current ED Register */
#define HC_DHR 0x00000030 /* HC Done Head Register */
/* Frame Counter Partition */
#define HC_FIR 0x00000034 /* HC Frame Interval Register */
#define HC_FRR 0x00000038 /* HC Frame Remaining Register */
#define HC_FNR 0x0000003C /* HC Frame Number Register */
#define HC_PSR 0x00000040 /* HC Period Start Register */
#define HC_LSTR 0x00000044 /* HC LS Threshold Register */
/* Root Hub Partition */
#define HC_RHDAR 0x00000048 /* HC Root Hub Descriptor A Register */
#define HC_RHDBR 0x0000004C /* HC Root Hub Descriptor B Register */
#define HC_RHSR 0x00000050 /* HC Root Hub Status Register */
#define HC_RHPSR(_n) (0x00000054 + (_n) * 4) /* HC Root Hub Port Status Register */
/* HC Revision Register Bit Definitions */
#define HC_RR_REV_MASK 0x000000FFL /* Revision */
/* HC Control Register Bit Definitions */
#define HC_CR_CBSR_MASK 0x00000003L /* Control Bulk Service Ratio */
#define HC_CR_CBSR_1_1 0x00000000L /* 1:1 */
#define HC_CR_CBSR_2_1 0x00000001L /* 2:1 */
#define HC_CR_CBSR_3_1 0x00000002L /* 3:1 */
#define HC_CR_CBSR_4_1 0x00000003L /* 4:1 */
#define HC_CR_PLE 0x00000004L /* Periodic List Enable */
#define HC_CR_IE 0x00000008L /* Isochrounous Enable */
#define HC_CR_CLE 0x00000010L /* Control List Enable */
#define HC_CR_BLE 0x00000020L /* Bulk List Enable */
#define HC_CR_HCFS_MASK 0x000000C0L /* Host Controller Functional State */
#define HC_CR_HCFS_RESET 0x00000000L /* USB Reset */
#define HC_CR_HCFS_RESUME 0x00000040L /* USB Resume */
#define HC_CR_HCFS_OPERATIONAL 0x00000080L /* USB Operational */
#define HC_CR_HCFS_SUSPEND 0x000000C0L /* USB Suspend */
#define HC_CR_IR 0x00000100L /* Interrupt Routing */
#define HC_CR_RWC 0x00000200L /* Remote Wakeup Connected */
#define HC_CR_RWE 0x00000400L /* Remote Wakeup Enable */
/* HC Command Status Register Bit Definitions */
#define HC_CSR_HCR 0x00000001L /* Host Controller S/W Reset */
#define HC_CSR_CLF 0x00000002L /* Control List Filled */
#define HC_CSR_BLF 0x00000004L /* Bulk List Filled */
#define HC_CSR_OCR 0x00000008L /* Ownership Change Request */
#define HC_CSR_SOC_MASK 0x00030000L /* Schedulling Overrun Count */
#define HC_CSR_SOC_SHIFT 16
/* HC Interrupt Status/Enable/Disable Register Bit Definitions */
#define HC_INT_SO 0x00000001L /* Schedulling Overrun Interrupt */
#define HC_INT_WDH 0x00000002L /* Writeback Done Head Interrupt */
#define HC_INT_SF 0x00000004L /* Start of Frame Interrupt */
#define HC_INT_RD 0x00000008L /* Resume Detected Interrupt */
#define HC_INT_UE 0x00000010L /* Unrecoverable Error Interrupt */
#define HC_INT_FNO 0x00000020L /* Frame Number Overflow Interrupt */
#define HC_INT_RHSC 0x00000040L /* Root Hub Status Change Interrupt */
#define HC_INT_OC 0x40000000L /* Ownership Change Interrupt */
#define HC_INT_MIE 0x80000000L /* Master Interrupt */
/* HC Frame Interval Register Bit Definitions */
#define HC_FIR_FI_MASK 0x00003FFFL /* Frame Interval */
#define HC_FIR_FSMPS_MASK 0x7FFF0000L /* FS Largest Data Packet */
#define HC_FIR_FSMPS_SHIFT 16
#define HC_FIR_FIT 0x80000000L /* Frame Interval Toggle */
#define HC_FIR_FI_FS 11999 /* Full Speed Default Frame Interval, 11.999 Mbps */
#define HC_FIR_FI_LS 1576 /* Low Speed Default Frame Interval, 1.576 Mbps */
/* HC Frame Remaining Register Bit Definitions */
#define HC_FRR_FR_MASK 0x00003FFFL /* Frame Remaining */
#define HC_FRR_FRT 0x80000000L /* Frame Remaining Toggle */
/* HC Frame Number Register Bit Definitions */
#define HC_FNR_FN_MASK 0x0000FFFFL /* Frame Number */
/* HC Period Start Register Bit Definitions */
#define HC_PSR_PS_MASK 0x00003FFFL /* Period Start */
/* HC Low Speed Threshold Register Bit Definitions */
#define HC_LSTR_LST_MASK 0x00000FFFL /* LS Threshold */
/* HC Root Hub Descriptor A Register Bit Definitions */
#define HC_RHDAR_NDP_MASK 0x000000FFL /* Number Downstream Ports */
#define HC_RHDAR_PSM 0x00000100L /* Power Switching Mode */
#define HC_RHDAR_NPS 0x00000200L /* No Power Switching */
#define HC_RHDAR_COMP 0x00000400L /* Compound Device */
#define HC_RHDAR_OCPM 0x00000800L /* Over Current Protection Mode */
#define HC_RHDAR_NOCP 0x00001000L /* No Over Current Protection */
#define HC_RHDAR_POTPGT_MASK 0xFF000000L /* Power On To Power Good Time */
#define HC_RHDAR_POTPGT_SHIFT 24
/* HC Root Hub Descriptor B Register Bit Definitions */
#define HC_RHDBR_DR_MASK 0x0000FFFFL /* Device Removable */
#define HC_RHDBR_PPCM_MASK 0xFFFF0000L /* Port Power Control Mask */
#define HC_RHDBR_PPCM_SHIFT 16
#define HC_MAX_ROOT_PORT 15 /* Root Hub Port, 0:reserved, 1 ~ 15 */
/* HC Root Hub Status Register Bit Definitions */
#define HC_RHSR_LPS 0x00000001L /* Local Power Status */
#define HC_RHSR_OCI 0x00000002L /* Over Current Indicator */
#define HC_RHSR_DRWE 0x00008000L /* Device Remote Wakeup Enable */
#define HC_RHSR_LPSC 0x00010000L /* Local Power Status Change */
#define HC_RHSR_OCIC 0x00020000L /* Over Current Indicator Change */
#define HC_RHSR_CRWE 0x80000000L /* Clear Remote Wakeup Enable */
/* HC Root Hub Port Status Register Bit Definitions */
#define HC_RHPSR_CCS 0x00000001L /* Current Connect Status */
#define HC_RHPSR_PES 0x00000002L /* Port Enable Status */
#define HC_RHPSR_PSS 0x00000004L /* Port Suspend Status */
#define HC_RHPSR_POCI 0x00000008L /* Port Over Current Indicator */
#define HC_RHPSR_PRS 0x00000010L /* Port Reset Status */
#define HC_RHPSR_PPS 0x00000100L /* Port Power Status */
#define HC_RHPSR_LSDA 0x00000200L /* Low Speed Device Attached */
#define HC_RHPSR_SC_MASK 0xFFFF0000L /* Status Change */
#define HC_RHPSR_CSC 0x00010000L /* Connect Status Change */
#define HC_RHPSR_PESC 0x00020000L /* Port Enable Status Change */
#define HC_RHPSR_PSSC 0x00040000L /* Port Suspend Status Change */
#define HC_RHPSR_OCIC 0x00080000L /* Port Over Current Indicator Change */
#define HC_RHPSR_PRSC 0x00100000L /* Port Reset Status Change */
/* HC Endpoint Descriptor */
typedef struct _HC_ENDPOINT_DESCRIPTOR {
ULONG Control; /* Control Bits */
ULONG TailP; /* TD Queue Tail Pointer */
ULONG HeadP; /* TD Queue Head Pointer */
ULONG NextED; /* Next ED */
} HC_ENDPOINT_DESCRIPTOR, *PHC_ENDPOINT_DESCRIPTOR;
#define HC_ED_ALIGN 16 /* ED must be aligned to a 16-byte boundary */
#define HC_ED_FA_MASK 0x0000007FL /* Function Address */
#define HC_ED_EN_MASK 0x00000780L /* Endpoint Number */
#define HC_ED_EN_SHIFT 7
#define HC_ED_D_TD 0x00000000L /* Direction From TD */
#define HC_ED_D_OUT 0x00000800L /* Direction Out */
#define HC_ED_D_IN 0x00001000L /* Direction In */
#define HC_ED_S 0x00002000L /* Speed, 1=low-speed, 0=full-speed */
#define HC_ED_K 0x00004000L /* Skip */
#define HC_ED_F 0x00008000L /* Format, 1=Iso TD, 0=Gen TD */
#define HC_ED_MPS_MASK 0x07FF0000L /* Maximum Packet Size */
#define HC_ED_MPS_SHIFT 16
#define HC_ED_TDQ_STATUS_MASK 0x00000003L /* TD Queue Status */
#define HC_ED_TDQ_H 0x00000001L /* Halted */
#define HC_ED_TDQ_C 0x00000002L /* Toggle Carry */
/* HC General Transfer Descriptor */
typedef struct _HC_TRANSFER_DESCRIPTOR {
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