_s5l5005.h

SAMSUNG 5009的源代码

/* s5l5005.h - SAMSUNG S5L5005 header file */

/* Copyright 2005 SAMSUNG Electronics. */

/*
modification history
--------------------
02e,28nov05,jmLee   version control sync.
01a,21sep05,?????   created.
*/


#ifndef __INCs5l5005h
#define __INCs5l5005h

#ifdef  __cplusplus
extern  "C" {
#endif


#ifndef S5L5005ABBREVIATIONS
#define S5L5005ABBREVIATIONS

#ifdef   _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile char VINT8;                                /* volatile unsigned byte */
typedef volatile short VINT16;                              /* volatile unsigned halfword */
typedef volatile long VINT32;                               /* volatile unsigned word */
typedef volatile unsigned char VUINT8;                      /* volatile unsigned byte */
typedef volatile unsigned short VUINT16;                    /* volatile unsigned halfword */
typedef volatile unsigned long VUINT32;                     /* volatile unsigned word */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* S5L5005ABBREVIATIONS */


/* S5L5005 ASIC Base Address */

#define S5L5005_REG_BASE_ADRS           0x38000000          /* Internal Register Base Address */
#define S5L5005_REG_SIZE                0x08000000          /* Internal Register Size */

#define REG_32(_off)                    (CAST(VUINT32 *)(S5L5005_REG_BASE_ADRS + _off))
#define REG_16(_off)                    (CAST(VUINT16 *)(S5L5005_REG_BASE_ADRS + _off))
#define REG_8(_off)                     (CAST(VUINT8  *)(S5L5005_REG_BASE_ADRS + _off))


/*******************************************************************************
        S5L5005 Intrrupt Controller Registers
*******************************************************************************/

#define S5L5005_INTSRCPND               REG_32(0x01C00000)  /* Interrupt Source Pending Register */
#define S5L5005_INTMOD                  REG_32(0x01C00004)  /* Interrupt Mode Register */
#define S5L5005_INTMASK                 REG_32(0x01C00008)  /* Interrupt Mask Register */
#define S5L5005_INTPRIORITY             REG_32(0x01C0000C)  /* Interrupt Priority Register */
#define S5L5005_INTPND                  REG_32(0x01C00010)  /* Interrupt Pending Register */
#define S5L5005_INTOFFSET               REG_32(0x01C00014)  /* Interrupt Offset Register */
#define S5L5005_EINTPOL                 REG_32(0x01C00018)  /* External Interrupt Polarity Selection Register */
#define S5L5005_EINTPEND                REG_32(0x01C0001C)  /* External Interrupt Pending Register */
#define S5L5005_EINTMASK                REG_32(0x01C00020)  /* External Interrupt Mask Register */

/* Internal Interrupt Mode/Mask Register Bit Definitions */

#define S5L8700_INT_31                  0x80000000          /* Reserved */
#define S5L5005_INT_TSTAMP              0x40000000          /* UART1 Tx/Rx Interrupt */
#define S5L5005_INT_SDCI                0x20000000          /* Nand-Flash Controller Interrupt */
#define S5L5005_INT_MSTICK              0x10000000          /* Memory Stick Interrupt */
#define S5L5005_INT_IIC                 0x08000000          /* I2C Interrupt */
#define S5L5005_INT_SPI                 0x04000000          /* SPI Interrupt */
#define S5L5005_INT_ADM                 0x02000000          /* Audio DSP Interrupt */
#define S5L8700_INT_24                  0x0100000           /* Reserved */
#define S5L5005_INT_SPDIF               0x00800000          /* SPDIF Interrupt */
#define S5L5005_INT_UART0               0x00400000          /* UART0 Tx/Rx Interrupt */
#define S5L8700_INT_21                  0x00200000          /* Reserved */
#define S5L5005_INT_FIU                 0x00100000          /* Front Interface Unit Interrupt (ATAPI) */
#define S5L5005_INT_PSD                 0x00080000          /* Program Stream Demux Interrupt */
#define S5L5005_INT_SPD                 0x00040000          /* Sub-Picture Decoder Interrupt */
#define S5L5005_INT_M2VD                0x00020000          /* MPEG Video Decoder Interrupt  */
#define S5L8700_INT_16                  0x00010000          /* Reserved */
#define S5L5005_INT_MIXER               0x00008000          /* Mixer Interrupt */
#define S5L5005_INT_GA                  0x00004000          /* Graphic Accelerator Interrupt */
#define S5L5005_INT_CSDMA               0x00002000          /* BT.656 Interrupt */
#define S5L5005_INT_NTSC                0x00001000          /* NTSC/PAL Encoder Interrupt */
#define S5L5005_INT_ATAPI               0x00000800          /* DMA 1-3 Interrupt */
#define S5L5005_INT_DMA0                0x00000400          /* DMA 0 Interrupt */
#define S5L5005_INT_TIMER_D             0x00000200          /* Timer D Interrupt */
#define S5L5005_INT_TIMER_C             0x00000100          /* Timer C Interrupt */
#define S5L5005_INT_TIMER_B             0x00000080          /* Timer B Interrupt */
#define S5L5005_INT_WDT                 0x00000040          /* Watchdog Timer Interrupt */
#define S5L5005_INT_TIMER_A             0x00000020          /* Timer A Interrupt */
#define S5L5005_INT_EINTG               0x00000010          /* External Interrupt Group (3~7) */
#define S5L5005_INT_IR                  0x00000008          /* Remote Control Signal Interrupt */
#define S5L5005_INT_USB_HOST            0x00000004          /* USB Host Interrupt */
#define S5L8700_INT_1                   0x00000002          /* Reserved */
#define S5L5005_INT_EINT0               0x00000001          /* External Interrupt 0 */

/* External Interrupt Mode/Mask Register Bit Definitions */

#define S5L5005_INT_EXT7                0x00000080          /* External Interrupt 7 */
#define S5L5005_INT_EXT6                0x00000040          /* External Interrupt 6 */
#define S5L5005_INT_EXT5                0x00000020          /* External Interrupt 5 */
#define S5L5005_INT_EXT4                0x00000010          /* External Interrupt 4 */
#define S5L5005_INT_EXT3                0x00000008          /* External Interrupt 3 */
#define S5L5005_INT_EXT2                0x00000004          /* External Interrupt 2 */
#define S5L5005_INT_EXT1                0x00000002          /* External Interrupt 1 */
#define S5L5005_INT_EXT0                0x00000001          /* External Interrupt 0 */


#ifdef  __cplusplus
}
#endif

#endif  /* __INCs5l5005h */