wave.vhd

波形发生器的vhdl源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity WAVE  is 
port(
	  clk:in std_logic;
	  reset:in std_logic;
	 UA,UB,UC,IA,IB,IC: out std_logic
-- kf2: out std_logic_vector(15 downto 0);
     -- period2:out std_logic_vector(15 downto 0); 
--addcount1:out std_logic_vector(15 downto 0) ;
 --	aends1,bends1,cends1,cstarts1,bstarts1: out std_logic_vector(7 downto 0) 
     );end entity WAVE; 
	  

architecture WAVEarch of WAVE is 

Component pwm 
 port(clk:in std_logic;
     reset:in std_logic;
	 width:in std_logic_vector(15 downto 0);
     XHA,XLA,XHB,XLB,XHC,XLC:out std_logic;
	 addrctrl:out std_logic_vector(7 downto 0)
 --kf2: out std_logic_vector(15 downto 0);
-- addcount1:out std_logic_vector(15 downto 0) ;
 --period2:out std_logic_vector(15 downto 0); 
 	
--aends1,bends1,cends1,cstarts1,bstarts1: out std_logic_vector(7 downto 0)      
 	 );
 
  end Component pwm;

 

Component rom 
	PORT
	(   address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END Component rom;
 

 

	signal clks,resets,SIG1,SIG2,SIG3,SIG4,SIG5,SIG6:std_logic;
	signal widths :std_logic_vector(15 downto 0);
    signal addrctrls:std_logic_vector(7 downto 0);
 
   BEGIN
U1:pwm port map(clks,resets,widths,SIG1,SIG2,SIG3,SIG4,SIG5,SIG6,addrctrls);
u2:rom  port map(addrctrls,clks,widths);
	 clks<=clk;
   RESETS<=RESET;
  UA<=SIG1;
   UB<=SIG2;
  UC<=SIG3;
  IA<=SIG4;
  IB<=SIG5;
 IC<=SIG6;
  
end architecture WAVEarch;