interrupt.c

ct952 source code use for Digital Frame Photo

    // irint (10:2)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_IR )
    {
#ifndef NO_IR
        ISR_IRSaveClearStatus( );
#endif //#ifndef NO_IR
    }
    // atapi_int (10:3) / stb_underflow (10:4)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_STBBUF_UNDERFLOW )
    {
    }
    // biu_int (10:4)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_BIU )
    {
#ifndef NO_PARSER
        ISR_BIUSaveClearStatus( );
#endif  //#ifndef NO_PARSER
    }
    // bsrdint (10:5) and abufint_overflow (10:11)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & (INT_PROC1_2ND_MCU_BSRD|INT_PROC1_2ND_ABUF_OVERFLOW) )
    {
#ifndef NO_PARSER
        ISR_BSRD_ABUFSaveClearStatus( );
#endif  //#ifndef NO_PARSER
    }
    // eccrdint (10:6)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_MCU_ECCRD )
    {
    }
    // edcrdint (10:7)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_MCU_EDCRD )
    {
    }
    // osdrdint (10:8)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_MCU_OSDRD )
    {
    }
    // vbufint_overflow (10:9)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_VBUF_OVERFLOW )
    {
#ifndef NO_DECODER
        ISR_VBUF_OF_SaveClearStatus( );
#endif  //#ifndef NO_DECODER
    }
    // vbufint_underflow (10:10)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_VBUF_UNDERFLOW )
    {
#ifndef NO_DECODER
        ISR_VBUF_UF_SaveClearStatus( );
#endif  //#ifndef NO_DECODER
    }
    // sp1bufint_overflow (10:12)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_SP1BUF_OVERFLOW )
    {
    }
    // sp2bufint_overflow (10:13)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_SP2BUF_OVERFLOW )
    {
    }
    // stbbufint_overflow (10:14)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_STBBUF_OVERFLOW )
    {
    }
    // int_osd_underflow (10:15)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_OSD_UNDERFLOW )
    {
    }
    // int_osd_error (10:16)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_OSD_ERR )
    {
    }
    // int_main_under (10:17)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_MAIN_UNDER )
    {
    }
    // int_sp (10:18)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_SP_ERR )
    {
    }
    // pla_err (10:19)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_PLA_ERR )
    {
    }
    // wrprotint (10:20)
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_MCU_WR_PROTECTION )
    {
    }
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_VPU )
    {
    }
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_ERR_CNT )
    {
    }
    if( __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & INT_PROC1_2ND_PANEL_IR )
    {
    }


    // clear secondary mask pendding interrupts
    REG_PLAT_PROC1_2ND_INT_CLEAR = __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING;

#ifdef INT_STAT
    dwLoop = 0;
    while (__INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING != 0)
    {
        __dwINT2_Stat[dwLoop] += __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING & 0x1;
        dwLoop++;
        __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING >>= 1;
    }
#endif

    // clear fisrt mask pendding interrupt 10
    REG_PLAT_INT_CLEAR = (1 << INT_NO_PROC1_2ND);

    // Tell the processor that we have received
    // the interrupt.
    // cyg_interrupt_acknowledge( vector );

    if( __dwINTISRCounter[INT_NO10] )
    {
        // process ISR routines one by one
        for( dwLoop = 0; dwLoop < __dwINTISRCounter[INT_NO10]; dwLoop ++ )
        {
            (*(__pINTISRRoutine[INT_NO10][dwLoop]))( );
        }
    }

#ifdef MEASURE_INT_TIME
    dwEndTime = REG_PLAT_TIMER2_COUNTER;
    __dwINT_Time_ISR[INT_NO10] = dwStartTime - dwEndTime;
    __dwINT_PENDING[INT_NO10] = __INTISRintProc12ndStatus.dwPLAT_PROC1_2ND_INT_PENDING;    
    if (dwEndTime > dwStartTime)
    {
        __dwINT_Time_ISR[INT_NO10] += 0xFFFFFF;
    }

    if (__dwINT_MaxTime_ISR[INT_NO10] < __dwINT_Time_ISR[INT_NO10])
    {
        __dwINT_MaxTime_ISR[INT_NO10] = __dwINT_Time_ISR[INT_NO10];
        __dwINT_MaxTime_PENDING[INT_NO10] = __dwINT_PENDING[INT_NO10];
    }
#endif

    // Tell the kernel that chained interrupt processing
    // is done and the DSR needs to be executed next.
    if( __dwINTDSRCounter[INT_NO10] )
    {
        // Block this interrupt from occurring until
        // the DSR completes.
        cyg_interrupt_mask( vector );

        return( CYG_ISR_HANDLED | CYG_ISR_CALL_DSR );
    }
    else
    {
        return( CYG_ISR_HANDLED );      // if no DSR needed to be executed
    }
}

//
// Deferred service routine for interrupt 10.
//
void    INT_Proc1_2nd_dsr(
        cyg_vector_t vector,
        cyg_ucount32 count,
        cyg_addrword_t data)
{
    DWORD   dwLoop;

#ifdef MEASURE_INT_TIME
    DWORD   dwStartTime;
    DWORD   dwEndTime;
    DWORD   dwTotalTime;

    dwStartTime = REG_PLAT_TIMER2_COUNTER;
#endif

    // process DSR routines one by one
    for( dwLoop = 0; dwLoop < __dwINTDSRCounter[INT_NO10]; dwLoop ++ )
    {
        (*(__pINTDSRRoutine[INT_NO10][dwLoop]))( );
    }

#ifdef MEASURE_INT_TIME
    dwEndTime = REG_PLAT_TIMER2_COUNTER;
    dwTotalTime = dwStartTime - dwEndTime;
    if (dwEndTime > dwStartTime)
    {
        dwTotalTime += 0xFFFFFF;
    }

    if (__dwINT_MaxTime_DSR[INT_NO10] < dwTotalTime)
    {
        __dwINT_MaxTime_DSR[INT_NO10] = dwTotalTime;
    }
    
    if (__dwINT_MaxTotalTime[INT_NO10] < (dwTotalTime + __dwINT_Time_ISR[INT_NO10]))
    {
        __dwINT_MaxTotalTime[INT_NO10] = (dwTotalTime + __dwINT_Time_ISR[INT_NO10]);
        __dwINT_MaxTotalTime_PENDING[INT_NO10] = __dwINT_PENDING[INT_NO10];
    }    

    if (__dwTotalCnt[INT_NO10] < 10000)
    {
        __wINT_TotalTime2[__dwTotalCnt[INT_NO10]++] = (dwTotalTime + __dwINT_Time_ISR[INT_NO10]);
    }
#endif
    // Allow this interrupt to occur again.
    cyg_interrupt_unmask( vector );
}

cyg_uint32  INT_Proc1_SW_isr(
        cyg_vector_t vector,
        cyg_addrword_t data)
{
    MACRO_PLAT_KEY_LOCK( );
    __INTISRintProc1SWStatus.dwPLAT_PARAMETER3 = REG_PLAT_PARAMETER3;
    REG_PLAT_PARAMETER3 = PLAT_CMDID_NULL;
    MACRO_PLAT_KEY_UNLOCK( );

    // Block this interrupt from occurring until
    // the DSR completes.
    cyg_interrupt_mask( vector );

    // Tell the processor that we have received
    // the interrupt.
    // cyg_interrupt_acknowledge( vector );

    return( CYG_ISR_HANDLED | CYG_ISR_CALL_DSR );
}

//
// Deferred service routine for interrupt 11 (software interrupt).
//
void    INT_Proc1_SW_dsr(
        cyg_vector_t vector,
        cyg_ucount32 count,
        cyg_addrword_t data)
{
#ifndef AP_FRAMEWORK
    printf("\nSW_INT Issue: %lx", __INTISRintProc1SWStatus.dwPLAT_PARAMETER3);
    // Chuan0.68, PROC2 will interrupt PROC1 when STC Updated
    if (__INTISRintProc1SWStatus.dwPLAT_PARAMETER3 == PLAT_CMDID_STCUPDATED)
    {
        // LLY1.02, unfreeze the STC if CDROM motion w/ skip video stream mode
        // Since, it's audio master mode, must unfreeze STC, then DSP update can be done.
        if( (__bAttrPlay&TYPE_CDROM_AV) &&(__bVideoID==HAL_THROW_VIDEO) )
        {
            DISP_STCFreeze(0, DISP_UNFREEZE_STC);
        }
        __dwNewSTCStatus |= DISP_AUDIO_STC_UPDATED;
        __dwSTCUpdated = TRUE;
        __SPUCtrl.bEnable |= SPCTRL_REALPTS; // Enable SP Decoder before update STC.
#ifdef DEBUG_AVSYNC
        DBG_Printf(DBG_DSR, DBG_INFO_PRINTF, "AUDIO: STC Updated!!(%lx), VPTS: %lx", REG_PLAT_TIMER3_VALUE, __dwDISP_PTS);
#endif
    }
#endif  //#ifndef AP_FRAMEWORK

    // Allow this interrupt to occur again.
    cyg_interrupt_unmask( vector );
}

#ifdef EMU_RTC
//Aron2.77, added for DMP SW-RTC
cyg_uint32  INT_Timer2_isr(
        cyg_vector_t vector,
        cyg_addrword_t data)
{
    cyg_interrupt_mask( vector );
    return( CYG_ISR_HANDLED | CYG_ISR_CALL_DSR );
 }

void   INT_Timer2_dsr(
        cyg_vector_t vector,
        cyg_ucount32 count,
        cyg_addrword_t data)
{
    extern ULONGLONG __u64SystemTick2;
    __u64SystemTick2 += 1;
    cyg_interrupt_unmask( vector );    
}
#endif

void    INT_Init( void )
{
#ifdef MEASURE_INT_TIME
    REG_PLAT_TIMER2_RELOAD = 0x00ffffff;
    REG_PLAT_TIMER2_CONTROL = 0x3;
#endif
    
    //
    // Create interrupt 13.
    //
    cyg_interrupt_create(
            CYGNUM_HAL_INTERRUPT_13,
            CYGNUM_HAL_PRI_HIGH,
            0,
            &INT_Proc1_1st_isr,
            &INT_Proc1_1st_dsr,
            &_INTPROC11stHandle,
            &_INTPROC11st);

    // Attach the interrupt created to the vector.
    cyg_interrupt_attach( _INTPROC11stHandle );

    //
    // Create interrupt 11.
    //
    cyg_interrupt_create(
            CYGNUM_HAL_INTERRUPT_11,
            CYGNUM_HAL_PRI_HIGH,
            0,
            &INT_Proc1_SW_isr,
            &INT_Proc1_SW_dsr,
            &_INTPROC1SWHandle,
            &_INTPROC1SW);

    // Attach the interrupt created to the vector.
    cyg_interrupt_attach( _INTPROC1SWHandle );

    //
    // Create interrupt 10.
    //
    cyg_interrupt_create(
            CYGNUM_HAL_INTERRUPT_10,
            CYGNUM_HAL_PRI_HIGH,
            0,
            &INT_Proc1_2nd_isr,
            &INT_Proc1_2nd_dsr,
            &_INTPROC12ndHandle,
            &_INTPROC12nd);

    // Attach the interrupt created to the vector.
    cyg_interrupt_attach( _INTPROC12ndHandle );

#ifdef EMU_RTC
//Aron2.77, added for DMP SW-RTC
    cyg_interrupt_create(
            CYGNUM_HAL_INTERRUPT_9,
            CYGNUM_HAL_PRI_HIGH,
            0,
            &INT_Timer2_isr,
            &INT_Timer2_dsr,
            &__INTTIMER2Handle,
            &__INTTIMER2);
    
    cyg_interrupt_attach( __INTTIMER2Handle );
    cyg_interrupt_unmask( CYGNUM_HAL_INTERRUPT_9 );            
#endif    
    
    // Unmask the interrupt we just configured.
    cyg_interrupt_unmask( CYGNUM_HAL_INTERRUPT_13 );
    cyg_interrupt_unmask( CYGNUM_HAL_INTERRUPT_11 );
    cyg_interrupt_unmask( CYGNUM_HAL_INTERRUPT_10 );
}

VOID    INT_VSYNC_End(VOID)
{
#ifdef SUPPORT_STB
{
    extern VOID DVB_TTX_Vsync(VOID);
    DVB_TTX_Vsync();
}
#endif
}