ctkav_sdc.h

ct952 source code use for Digital Frame Photo

#define SDC_STAT_CMD_SIG                        (1 << 24)
#define SDC_STAT_DAT_SIG(n)                     (1 << (20 + (n)))
#define SDC_STAT_DAT_SIG0                       SDC_STAT_DAT_SIG(0)
#define SDC_STAT_DAT_SIG1                       SDC_STAT_DAT_SIG(1)
#define SDC_STAT_DAT_SIG2                       SDC_STAT_DAT_SIG(2)
#define SDC_STAT_DAT_SIG3                       SDC_STAT_DAT_SIG(3)
#define SDC_STAT_WP_PIN                         (1 << 19)
#define SDC_STAT_CD_PIN                         (1 << 18)
#define SDC_STAT_CARD_STAT_STABLE               (1 << 17)
#define SDC_STAT_CARD_INS                       (1 << 16)
#define SDC_STAT_BUFF_READ_ENABLE               (1 << 11)
#define SDC_STAT_BUFF_WRITE_ENABLE              (1 << 10)
#define SDC_STAT_READ_TRAN_ACTIVE               (1 << 9)
#define SDC_STAT_WRITE_TRAN_ACTIVE              (1 << 8)
#define SDC_STAT_DAT_LINE_ACTIVE                (1 << 2)
#define SDC_STAT_CMD_INHIBIT_DAT                (1 << 1)
#define SDC_STAT_CMD_INHIBIT_CMD                (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_HOST_CTRL
#define SDC_HOST_CTRL_HIGH_SPEED                (1 << 2)
#define SDC_HOST_CTRL_4BIT                      (1 << 1)
#define SDC_HOST_CTRL_LED_ON                    (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_PW_CTRL
#define SDC_PW_CTRL_BUS_VOL(n)                  ((((WORD)(n)) & 7) << 1)
#define SDC_PW_CTRL_BUS_VOL_33V                 SDC_PW_CTRL_BUS_VOL(7)
#define SDC_PW_CTRL_BUS_VOL_30V                 SDC_PW_CTRL_BUS_VOL(6)
#define SDC_PW_CTRL_BUS_VOL_18V                 SDC_PW_CTRL_BUS_VOL(5)
#define SDC_PW_CTRL_BUS_PW_ON                   (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_BLK_GAP_CTRL
#define SDC_BLK_GAP_CTRL_INT_AT_BLK_GAP         (1 << 3)
#define SDC_BLK_GAP_CTRL_READ_WAIT_CTRL         (1 << 2)
#define SDC_BLK_GAP_CTRL_CONT_REQ               (1 << 1)
#define SDC_BLK_GAP_CTRL_STOP_AT_BLK_GAP_REQ    (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_WAKEUP_CTRL
#define SDC_WAKEUP_CTRL_CARD_REM                (1 << 2)
#define SDC_WAKEUP_CTRL_CARD_INS                (1 << 1)
#define SDC_WAKEUP_CTRL_CARD_INT                (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_CLK_CTRL
#define SDC_CLK_CTRL_SDCLK_FREQ_SEL(n)          ((((WORD)(n)) & 0xff) << 8)
#define SDC_CLK_CTRL_SDCLK_ENABLE               (1 << 2)
#define SDC_CLK_CTRL_INCLK_STABLE               (1 << 1)
#define SDC_CLK_CTRL_INCLK_ENABLE               (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_TIMEOUT_CTRL
#define SDC_TIMEOUT_CTRL_DATA_TIMEOUT(n)        ((n) & 0xf)

// -------------------------------------------------------------------------------------------------
// REG_SDC_SW_RESET
#define SDC_SW_RESET_DAT_LINE                   (1 << 2)
#define SDC_SW_RESET_CMD_LINE                   (1 << 1)
#define SDC_SW_RESET_ALL                        (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_INT_STAT, REG_SDC_INT_STAT_ENABLE, REG_SDC_INT_ENABLE
#define SDC_INT_ERR_INT                         (1 << 31)
#define SDC_INT_CARD_INT                        (1 << 24)
#define SDC_INT_CARD_REM                        (1 << 23)
#define SDC_INT_CARD_INS                        (1 << 22)
#define SDC_INT_BUFF_READ_RDY                   (1 << 21)
#define SDC_INT_BUFF_WRITE_RDY                  (1 << 20)
#define SDC_INT_DMA_INT                         (1 << 19)
#define SDC_INT_BLK_GAP_EVENT                   (1 << 18)
#define SDC_INT_TRAN_COMPLETE                   (1 << 17)
#define SDC_INT_CMD_COMPLETE                    (1 << 16)
#define SDC_INT_ERR_VENDOR_SPEC_STAT(n)         ((1 << ((n) + 12)) & 0xf000)
#define SDC_INT_ERR_AUTO_CMD12                  (1 << 8)
#define SDC_INT_ERR_CURR_LIMIT                  (1 << 7)
#define SDC_INT_ERR_DATA_END_BIT                (1 << 6)
#define SDC_INT_ERR_DATA_CRC                    (1 << 5)
#define SDC_INT_ERR_DATA_TIMEOUT                (1 << 4)
#define SDC_INT_ERR_CMD_IDX                     (1 << 3)
#define SDC_INT_ERR_CMD_END_BIT                 (1 << 2)
#define SDC_INT_ERR_CMD_CRC                     (1 << 1)
#define SDC_INT_ERR_CMD_TIMEOUT                 (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_AUTO_CMD12_ERR_STAT
#define SDC_AUTO_CMD12_ERR_STAT_CMD_NOT_ISSUED_BY_AUTO_CMD12_ERR (1 << 7)
#define SDC_AUTO_CMD12_ERR_STAT_IDX_ERR         (1 << 4)
#define SDC_AUTO_CMD12_ERR_STAT_END_BIT_ERR     (1 << 3)
#define SDC_AUTO_CMD12_ERR_STAT_CRC_ERR         (1 << 2)
#define SDC_AUTO_CMD12_ERR_STAT_TIMEOUT_ERR     (1 << 1)
#define SDC_AUTO_CMD12_ERR_STAT_NOT_EXECUTED    (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_CPBLT
#define SDC_CPBLT_VOL_18V                       (1 << 26)
#define SDC_CPBLT_VOL_30V                       (1 << 25)
#define SDC_CPBLT_VOL_33V                       (1 << 24)
#define SDC_CPBLT_SUSPEND_RESUME                (1 << 23)
#define SDC_CPBLT_DMA                           (1 << 22)
#define SDC_CPBLT_HIGH_SPEED                    (1 << 21)
#define SDC_CPBLT_MAX_BLK_LEN_MASK              (3 << 16)
#define SDC_CPBLT_MAX_BLK_LEN_2048              (2 << 16)
#define SDC_CPBLT_MAX_BLK_LEN_1024              (1 << 16)
#define SDC_CPBLT_MAX_BLK_LEN_512               (0 << 16)
#define SDC_CPBLT_BASE_CLK_FREQ_MASK            (0x3f << 8)
#define SDC_CPBLT_TIMEOUT_CLK_UNIT              (1 << 7)
#define SDC_CPBLT_TIMEOUT_CLK_FREQ_MASK         (0x3f << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_MAX_CURR_CPBLT
#define SDC_MAX_CURR_CPBLT_18V_MASK             (0xff << 16)
#define SDC_MAX_CURR_CPBLT_30V_MASK             (0xff << 8)
#define SDC_MAX_CURR_CPBLT_33V_MASK             (0xff << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_SLOT_INT_STAT
#define SDC_SLOT_INT_STAT_SLOT(n)               ((1 << (n)) & 0xff)

// -------------------------------------------------------------------------------------------------
// REG_SDC_HOST_VER
#define SDC_HOST_VER_VEND_VER_MASK              (0xff << 8)
#define SDC_HOST_VER_SPEC_VER_MASK              (0xff << 0)


// =================================================================================================
#ifdef __cplusplus
    }
#endif  // __cplusplus
#endif  // __CTKAV_SDC_H__