ctkav_sdc.h

ct952 source code use for Digital Frame Photo

#ifndef __CTKAV_SDC_H__
#define __CTKAV_SDC_H__
#ifdef __cplusplus
    extern "C" {
#endif  // __cplusplus


#ifndef REG_FCR_BASE

// =================================================================================================
#define REG_FCR_BASE                            (0xa0001000)
// -------------------------------------------------------------------------------------------------
#define REG_FCR_FUNC_CTRL                       (*(volatile DWORD*)(REG_FCR_BASE+0x00))
#define REG_FCR_CPBLT                           (*(volatile DWORD*)(REG_FCR_BASE+0x04))

// =================================================================================================
// REG_FCR_FUNC_CTRL
#define FCR_FUNC_CTRL_SW_MS_CD                  (1 << 27)
#define FCR_FUNC_CTRL_SW_SD_CD                  (1 << 26)
#define FCR_FUNC_CTRL_SW_SD_WP                  (1 << 25)
#define FCR_FUNC_CTRL_SW_CDWP_ENABLE            (1 << 24)
#define FCR_FUNC_CTRL_LITTLE_ENDIAN             (1 << 23)
#define FCR_FUNC_CTRL_SD_FLEXIBLE_CLK           (1 << 22)
#define FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE(n)     (((n) & 3) << 20)
#define FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE_MASK   FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE(-1)
#define FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE_512    FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE(3)
#define FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE_256    FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE(2)
#define FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE_128    FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE(1)
#define FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE_64     FCR_FUNC_CTRL_AHB_MAX_BURST_SIZE(0)
#define FCR_FUNC_CTRL_INT_OPT_STAT              (1 << 19)
#define FCR_FUNC_CTRL_INT_OPT_DMA               (1 << 18)
#define FCR_FUNC_CTRL_SD_PULLUP_RESISTOR        (1 << 17)
#define FCR_FUNC_CTRL_MMC_8BIT                  (1 << 16)
#define FCR_FUNC_CTRL_CD_DEBOUNCE_TIME(n)       (((n) & 0xf) << 12)
#define FCR_FUNC_CTRL_CD_DEBOUNCE_TIME_MASK     FCR_FUNC_CTRL_CD_DEBOUNCE_TIME(-1)
#define FCR_FUNC_CTRL_PW_UP_TIME(n)             (((n) & 0xf) << 8)
#define FCR_FUNC_CTRL_PW_UP_TIME_MASK           FCR_FUNC_CTRL_PW_UP_TIME(-1)
#define FCR_FUNC_CTRL_SD_SIG_PULLUP_TIME(n)     (((n) & 0xf) << 4)
#define FCR_FUNC_CTRL_SD_SIG_PULLUP_TIME_MASK   FCR_FUNC_CTRL_SD_SIG_PULLUP_TIME(-1)
#define FCR_FUNC_CTRL_MS_SIG_DELAY(n)           (((n) & 3) << 2)
#define FCR_FUNC_CTRL_MS_SIG_DELAY_MASK         FCR_FUNC_CTRL_MS_SIG_DELAY(-1)
#define FCR_FUNC_CTRL_SD_SIG_DELAY(n)           ((n) & 3)
#define FCR_FUNC_CTRL_SD_SIG_DELAY_MASK         FCR_FUNC_CTRL_SD_SIG_DELAY(-1)

// -------------------------------------------------------------------------------------------------
// REG_FCR_CPBLT
#define FCR_CPBLT_VOL_18V                       (1 << 18)
#define FCR_CPBLT_VOL_30V                       (1 << 17)
#define FCR_CPBLT_VOL_33V                       (1 << 16)
#define FCR_CPBLT_SD_BASE_CLK_FREQ(n)           (((n) & 0x3f) << 8)
#define FCR_CPBLT_SD_BASE_CLK_FREQ_MASK         FCR_CPBLT_SD_BASE_CLK_FREQ(-1)
#define FCR_CPBLT_SD_MAX_CURR_CPBLT(n)          ((n) & 0xff)
#define FCR_CPBLT_SD_MAX_CURR_CPBLT_MASK        FCR_CPBLT_SD_MAX_CURR_CPBLT(-1)

#endif  // REG_FCR_BASE


// =================================================================================================
#define REG_SDC_BASE                            (0xa0001100L)
// -------------------------------------------------------------------------------------------------
#define REG_SDC_DMA_ADDR                        (*(volatile DWORD*)(REG_SDC_BASE+0x00))
#define REG_SDC_BLK_SIZE                        (*(volatile  WORD*)(REG_SDC_BASE+0x04))
#define REG_SDC_BLK_COUNT                       (*(volatile  WORD*)(REG_SDC_BASE+0x06))
#define REG_SDC_ARG                             (*(volatile DWORD*)(REG_SDC_BASE+0x08))
#define REG_SDC_TRAN_MODE                       (*(volatile  WORD*)(REG_SDC_BASE+0x0c))
#define REG_SDC_CMD                             (*(volatile  WORD*)(REG_SDC_BASE+0x0e))
#define REG_SDC_RESP(n)                         (*(volatile DWORD*)(REG_SDC_BASE+0x10+4*((n)&3)))
#define REG_SDC_RESP0                           REG_SDC_RESP(0)
#define REG_SDC_RESP1                           REG_SDC_RESP(1)
#define REG_SDC_RESP2                           REG_SDC_RESP(2)
#define REG_SDC_RESP3                           REG_SDC_RESP(3)
#define REG_SDC_DATA_PORT                       (*(volatile DWORD*)(REG_SDC_BASE+0x20))
#define REG_SDC_STAT                            (*(volatile DWORD*)(REG_SDC_BASE+0x24))
#define REG_SDC_HOST_CTRL                       (*(volatile  BYTE*)(REG_SDC_BASE+0x28))
#define REG_SDC_PW_CTRL                         (*(volatile  BYTE*)(REG_SDC_BASE+0x29))
#define REG_SDC_BLK_GAP_CTRL                    (*(volatile  BYTE*)(REG_SDC_BASE+0x2a))
#define REG_SDC_WAKEUP_CTRL                     (*(volatile  BYTE*)(REG_SDC_BASE+0x2b))
#define REG_SDC_CLK_CTRL                        (*(volatile  WORD*)(REG_SDC_BASE+0x2c))
#define REG_SDC_TIMEOUT_CTRL                    (*(volatile  BYTE*)(REG_SDC_BASE+0x2e))
#define REG_SDC_SW_RESET                        (*(volatile  BYTE*)(REG_SDC_BASE+0x2f))
#define REG_SDC_INT_STAT                        (*(volatile DWORD*)(REG_SDC_BASE+0x30))
#define REG_SDC_INT_STAT_ENABLE                 (*(volatile DWORD*)(REG_SDC_BASE+0x34))
#define REG_SDC_INT_ENABLE                      (*(volatile DWORD*)(REG_SDC_BASE+0x38))
#define REG_SDC_AUTO_CMD12_ERR_STAT             (*(volatile  WORD*)(REG_SDC_BASE+0x3c))
#define REG_SDC_CPBLT(n)                        (*(volatile DWORD*)(REG_SDC_BASE+0x40+4*(n)))
#define REG_SDC_CPBLT0                          REG_SDC_CPBLT(0)
#define REG_SDC_CPBLT1                          REG_SDC_CPBLT(1)
#define REG_SDC_MAX_CURR_CPBLT(n)               (*(volatile DWORD*)(REG_SDC_BASE+0x48+4*(n)))
#define REG_SDC_MAX_CURR_CPBLT0                 REG_SDC_MAX_CURR_CPBLT(0)
#define REG_SDC_MAX_CURR_CPBLT1                 REG_SDC_MAX_CURR_CPBLT(1)
#define REG_SDC_SLOT_INT_STAT                   (*(volatile  WORD*)(REG_SDC_BASE+0xfc))
#define REG_SDC_HOST_VER                        (*(volatile  WORD*)(REG_SDC_BASE+0xfe))

// =================================================================================================
// REG_SDC_BLK_SIZE
#define SDC_BLK_SIZE_DMA_BUFF_BND(n)            ((WORD)((n) & 7) << 12)
#define SDC_BLK_SIZE_DMA_BUFF_BND_MASK          SDC_BLK_SIZE_DMA_BUFF_BND(-1)
#define SDC_BLK_SIZE_DMA_BUFF_BND_512K          SDC_BLK_SIZE_DMA_BUFF_BND(7)
#define SDC_BLK_SIZE_DMA_BUFF_BND_256K          SDC_BLK_SIZE_DMA_BUFF_BND(6)
#define SDC_BLK_SIZE_DMA_BUFF_BND_128K          SDC_BLK_SIZE_DMA_BUFF_BND(5)
#define SDC_BLK_SIZE_DMA_BUFF_BND_64K           SDC_BLK_SIZE_DMA_BUFF_BND(4)
#define SDC_BLK_SIZE_DMA_BUFF_BND_32K           SDC_BLK_SIZE_DMA_BUFF_BND(3)
#define SDC_BLK_SIZE_DMA_BUFF_BND_16K           SDC_BLK_SIZE_DMA_BUFF_BND(2)
#define SDC_BLK_SIZE_DMA_BUFF_BND_8K            SDC_BLK_SIZE_DMA_BUFF_BND(1)
#define SDC_BLK_SIZE_DMA_BUFF_BND_4K            SDC_BLK_SIZE_DMA_BUFF_BND(0)
#define SDC_BLK_SIZE_TRAN_BLK_SIZE(n)           ((WORD)((n) & 0xfff))

// -------------------------------------------------------------------------------------------------
// REG_SDC_TRAN_MODE
#define SDC_TRAN_MODE_MULT_BLK                  (1 << 5)
#define SDC_TRAN_MODE_READ                      (1 << 4)
#define SDC_TRAN_MODE_AUTO_CMD12                (1 << 2)
#define SDC_TRAN_MODE_BLK_COUNT                 (1 << 1)
#define SDC_TRAN_MODE_DMA                       (1 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_CMD
#define SDC_CMD_IDX(n)                          ((((WORD)(n)) & 0x3f) << 8)
#define SDC_CMD_TYPE_ABORT                      (3 << 6)
#define SDC_CMD_TYPE_RESUME                     (2 << 6)
#define SDC_CMD_TYPE_SUSPEND                    (1 << 6)
#define SDC_CMD_TYPE_NORMAL                     (0 << 6)
#define SDC_CMD_DATA_PRESENT                    (1 << 5)
#define SDC_CMD_IDX_CHK                         (1 << 4)
#define SDC_CMD_CRC_CHK                         (1 << 3)
#define SDC_CMD_RESP_TYPE_LEN_0                 (0 << 0)
#define SDC_CMD_RESP_TYPE_LEN_136               (1 << 0)
#define SDC_CMD_RESP_TYPE_LEN_48                (2 << 0)
#define SDC_CMD_RESP_TYPE_LEN_48_BUSY_CHK       (3 << 0)

// -------------------------------------------------------------------------------------------------
// REG_SDC_STAT