hsystem.c

ct952 source code use for Digital Frame Photo

    HAL_UART_Disable(HAL_UART2);
#endif  // #ifdef IOMUTE_UART2_SAME_PORT

    // LLY2.13, using general define for HWMUTE GPIO group/ pin
    // LLY2.18, add procedure for new IO mute control
#ifdef  IOMUTE_ACTIVE_LOW
    // Mute: send value 0
    // DeMute: set pin as input mode while it w/ poll-high 5V or
    // DeMute: send value 1
    if(bMute)
    {
        HAL_WriteGPIO(HWMUTE_GPIO_GRP, PIN_HWMUTE, 0);
    }
    else
    {
        // LLY2.38, support different method for de-mute action base on if add pull-high 5V circuit
#ifdef  IOMUTE_NOT_ADD_PULL_HIGH_5V
        // If not add pll-high 5V circuit, just set output mode w/ value 1
        HAL_WriteGPIO(HWMUTE_GPIO_GRP, PIN_HWMUTE, 1);
#else   // #ifdef IOMUTE_NOT_ADD_PULL_HIGH_5V
        // Use "read GPIO" procedure to configure the pin as input mode
        // while IO mute circuit w/ poll-high 5V
        HAL_ReadGPIO(HWMUTE_GPIO_GRP, PIN_HWMUTE);
#endif  // #ifdef IOMUTE_NOT_ADD_PULL_HIGH_5V
    }
#else   // #ifdef IOMUTE_ACTIVE_LOW
    // Mute: send value as 1
    // DeMute: send value as 0
    if (bMute)
    {
        HAL_WriteGPIO( HWMUTE_GPIO_GRP, PIN_HWMUTE, 1);
    }
    else
    {
        HAL_WriteGPIO( HWMUTE_GPIO_GRP, PIN_HWMUTE, 0);
    }
#endif  // #ifdef IOMUTE_ACTIVE_LOW
}


// LLY2.04 create
//  ************************************************************************************
//  Function    :   HAL_GetDRAMSize
//  Description :   Get DRAM Size
//  Arguments   :   None
//  Return      :   HAL_DRAM_XXX, specify the DRAM size, the final size after down-grade
//                  The value is real DRAM end address
//  Notice      :
//  ************************************************************************************
DWORD HAL_GetDRAMSize(void)
{
    BYTE    bIndx;

    // Abstract DRAM type, bit[4:0]
    bIndx = (BYTE)(REG_PLAT_SYSTEM_CONFIGURATION1 & 0x1F);

    // If bit[4:3]=11, normal DRAM
    if( (bIndx & 0x18) == 0x18)
    {
        switch(bIndx)
        {
        case    0x1A:   // 32Mb, 2Mb x 16 (1x12x8 dram type)
        case    0x1F:   // 32Mb, 1Mb x 16 x 2 (1x11x8 cascade)
#ifdef CT909G_IC_SYSTEM//peteryu275, for support DRAM type, 2007/3/23 11:56AM
        case    0x18:   //32Mb, 2Mb x 16 ( 1x11x9 dram type)
#endif
            return (HAL_DRAM_32M);

        case    0x1E:   // 64Mb, 4Mb x 16 (2x12x8 dram type)
            return (HAL_DRAM_64M);

        case    0x1D:   // 128Mb, 8Mb x 16 (2x12x9 dram type)
            return (HAL_DRAM_128M);

        case    0x1C:   // 256Mb, 16Mb x 16 (2x13x9 dram type)
            return (HAL_DRAM_256M);

        case    0x1B:   // 16Mb, 1Mb x 16  (1x11x8 dram type)
            return (HAL_DRAM_16M);

        default:
            DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: Unknown DRAM type to decide DRAM size !\n");
            return (HAL_DRAM_UNKNOWN);
        }
    }
    // If bit[4:3]=01, 64M downgrade, let setting same as 32M
    else if(bIndx & 0x08)
    {
        return (HAL_DRAM_32M);
    }
    // If bit[4:3]=10, 128M downgrade, let setting same as 64M
    else if(bIndx & 0x10)
    {
       //return (HAL_DRAM_32M);
       return (HAL_DRAM_64M);//peteryu275, for support DRAM type, 2007/3/23 11:56AM
    }
    else
    {
        DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: Unknown DRAM type to decide DRAM size !\n");
        return (HAL_DRAM_UNKNOWN);
    }

}
//************************************************************************
// Description  :   Checksum
// Argument     :   dwStart: start addr (DWORD aligned)
//                  dwEnd: end addr (DWORD aligned)
// Return       :   checksum value
//************************************************************************
WORD HAL_CheckSum(DWORD dwStart, DWORD dwEnd) //test OK
{
    DWORD   dwAddr, dwMemValue;
    WORD    wResult = 0;
    for ( dwAddr=dwStart; dwAddr<dwEnd; dwAddr+=4)
    {
        dwMemValue = *((volatile DWORD *)dwAddr );
        wResult += (BYTE)((dwMemValue&0xFF000000)>>24);
        wResult += (BYTE)((dwMemValue&0x00FF0000)>>16);
        wResult += (BYTE)((dwMemValue&0x0000FF00)>> 8);
        wResult += (BYTE)( dwMemValue&0x000000FF);
    }
    return wResult;
}


// LLY2.15, define watch dog enable control bit
#define WATCHDOG_SINGAL_ENABLE  (1L<<28) //  REG_PLAT_SYSTEM_CONFIGURATION1 [28]

// LLY2.15, define the watch dog down count value
#define WATCHDOG_DOWN_COUNT_VALUE   0xA00000

// LLY2.15 create
//  ***************************************************************************
//  Function    :   HAL_WatchDog_Enable
//  Description :   Control Watch-Dog mechanism enable/ disable
//  Argument    :   TRUE, enable watch dog
//                  FALSE, disable watch dog
//  ***************************************************************************
void HAL_WatchDog_Enable(BYTE bEnable)
{
    DWORD   dwSaveInt;
#ifdef SUPPORT_WATCH_DOG
    DWORD   dwInitClk, dwCurClk, dwGap;

    //OS_DISABLE_INTERRUPTS( dwSaveInt );
    //MACRO_PLAT_KEY_LOCK( );

    if (bEnable)
    {
        REG_PLAT_WATCHDOG = WATCHDOG_DOWN_COUNT_VALUE;
        dwInitClk = REG_PLAT_TIMER1_COUNTER;

        // Here, we need idle time, (1 tick + 1/27MHz) ~= 2 ticks, to wait counter valid.
        while( TRUE )
        {
            MACRO_IDLE( );
            dwCurClk = REG_PLAT_TIMER1_COUNTER;
            dwGap = dwInitClk - dwCurClk;
            if( dwCurClk > dwInitClk )
            {
                dwGap += (REG_PLAT_PRESCALER_RELOAD + 1);
            }

            if( dwGap >= 2 )
            {
                break;
            }
        }

        OS_DISABLE_INTERRUPTS( dwSaveInt );
        MACRO_PLAT_KEY_LOCK( );

        REG_PLAT_SYSTEM_CONFIGURATION1 |= (WATCHDOG_SINGAL_ENABLE);
    }
    else
#endif // #ifdef SUPPORT_WATCH_DOG
    {
        OS_DISABLE_INTERRUPTS( dwSaveInt );
        MACRO_PLAT_KEY_LOCK( );
        REG_PLAT_SYSTEM_CONFIGURATION1 &= ~(WATCHDOG_SINGAL_ENABLE);
    }
    MACRO_PLAT_KEY_UNLOCK( );
    OS_RESTORE_INTERRUPTS( dwSaveInt );

}


//  ***************************************************************************
//  Function    :   HAL_WatchDog_Status
//  Description :   Report Watch-Dog disable/ enable status.
//  Arguments   :   None
//  Return      :   TRUE, watch dog is enabled.
//                  FALSE, watch dog is disabled
//  ***************************************************************************
BYTE HAL_WatchDog_Status(void)
{
#ifdef  SUPPORT_WATCH_DOG
    if(REG_PLAT_SYSTEM_CONFIGURATION1 & WATCHDOG_SINGAL_ENABLE)
    {
        return TRUE;
    }
#endif  // #ifdef SUPPORT_WATCH_DOG
    return FALSE;
}


//  ***************************************************************************
//  Function    :   HAL_WatchDog_Reset
//  Description :   Reset watch dog down count value as default
//  Argument    :   None
//  Return      :   None
//  ***************************************************************************
void HAL_WatchDog_Reset(void)
{
#ifdef  SUPPORT_WATCH_DOG
    REG_PLAT_WATCHDOG = WATCHDOG_DOWN_COUNT_VALUE;
#endif  // #ifdef SUPPORT_WATCH_DOG
}


// ***********************************************************************
//      Function        :   HAL_ClockSet
//      Description     :   Adjust Clock setting
//      Arguments       :   bMode:
//      Return          :   TRUE, the desired action is done
//                          FALSE, the desired action is fail
//      Side Effect     :
// ***********************************************************************
// LLY2.22, re-modify 2nd parameter type from BYTE to DWORD
// Since, caller may give CPU_SPEEd directly
// LLY2.36, re-modify this API since need return value to know the action ok or fail.
//void    HAL_ClockSet(BYTE bMode, DWORD dwType)
DWORD   HAL_ClockSet(BYTE bMode, DWORD dwType)
{
    DWORD dwCLK;

    switch(bMode)
    {
        case MODE_MPLL:
            // LLY2.36, call SPF_MPLLSet() to while using SPI Flash
            dwCLK = SPF_MPLLSet(dwType);
            if(dwCLK)
            {
                // Let IR checking method as polling while MPLL = 27MHz
                // Since, IR interupt must work >= 27MHz, and get from MPLL/2
                if(dwType == CPU_27M)
                {
                    INPUT_SetIRCheckMode(IR_CHECK_MODE_POLLING);
                }
                else
                {
                    INPUT_SetIRCheckMode(IR_CHECK_MODE_INT);
                }
            }
            return dwCLK;


        case MODE_APLL:
            // Ext_ACLK = 1, PD = 0, PF = 0, MF = 1, NF = 16 : Fout = 324
            REG_PLAT_APLL_CONTROL = (1 << 20) + (0 << 20) + (0 << 18) + (1 << 11) + (16);
            break;

// LLY2.56, don't support USB path for CT909G
// Notice: using ifndef CT909G IC to instead of USB source temporally
//         since compiler error if disable "SUPPORT_USB_SOURCE"
//#ifdef  SUPPORT_USB_SOURCE
#ifndef CT909G_IC_SYSTEM
        case MODE_UPLL:
            // PD = 0, PF = 0, MF = 1, NF = 14 : Fout = 288
            REG_PLAT_UPLL_CONTROL = (0 << 20) + (0 << 18) + (1 << 11) + (14);
            break;
#endif  // #ifdef SUPPORT_USB_SOURCE

        case MODE_CLKCTL_VIDEO:
            dwCLK = REG_PLAT_CLK_FREQ_CONTROL1;
            if ((dwType&TYPE_PSCAN) != TYPE_PSCAN)
            {
                dwCLK |= (1 << 24);
            }
            else
            {
                dwCLK &= ~(1 << 24);
            }
            REG_PLAT_CLK_FREQ_CONTROL1 = dwCLK;
            break;

        case MODE_CLKCTL_SERVO:
            break;
    }

    return TRUE;
}


// LLY2.61 create ...
#ifdef  SUPPORT_SCART_IF
#ifdef  SUPPORT_SCART_PWM_CTRL
//  *******************************************************************
//  Function    :   HAL_SCART_PWM_Init
//  Description :   Do SCART PWM related register initial
//  Arguments   :   bPort, specify the desired PWM port
//  Return      :   TRUE, the action is successfully
//                  FALSE, the action fail
//  *******************************************************************
BYTE HAL_SCART_PWM_Init(BYTE bPort)
{
    // Clear bit[5:4] first
    REG_PLAT_SYS_PIN_USE1 &= ~(0x3L<<4);

    if(bPort==SCART_PWM0)
    {
        // enable bit[4] to use SCART_PWM0
        REG_PLAT_SYS_PIN_USE1 |= (0x1L<<4);
    }
    else if(bPort==SCART_PWM1)
    {
        // enable bit[4] to use SCART_PWM0
        REG_PLAT_SYS_PIN_USE1 |= (0x1L<<5);
    }
    else
    {
        DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: not defined PWM ID\n");
        return FALSE;
    }

    return TRUE;
}


//  ******************************************************************************************
//  Function    :   HAL_SCART_PWM_Ctrl
//  Description :   Control SCART PWM related register
//  Arguments   :   bPort, specify the desired PWM port
//                  bVal, the value from 0 ~ 0xFF, used to specify the ratio while output 1
//                        ex, if give 0x7F, output ratio of 1 is 0x7F/0xFF = 1/2
//                            if give 0xFF, output ratio of 1 is 0xFF/0xFF = 1
//                            if give 0x0, output ratio of 1 is 0x0/0xFF = 0
//  Return      :   TRUE, the action is successfully
//                  FALSE, the action fail
//  ******************************************************************************************
BYTE HAL_SCART_PWM_Ctrl(BYTE bPort, BYTE bVal)
{
    if(bPort==SCART_PWM0)
    {
        REG_PLAT_SCART_PWM_CONFIGURATION &= ~(0xFFL);
        REG_PLAT_SCART_PWM_CONFIGURATION |= (0x1L<<12) + bVal;
    }
    else if(bPort==SCART_PWM1)
    {
        REG_PLAT_SCART_PWM_CONFIGURATION &= ~(0xFFL<<16);
        REG_PLAT_SCART_PWM_CONFIGURATION |= (0x1L<<28) + ((DWORD)bVal<<16);
    }
    else
    {
        DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: not defined PWM ID\n");
        return FALSE;
    }

    printf("PWM: %lx\n", bVal);
    return TRUE;
}

#endif  // #ifdef SUPPORT_SCART_PWM_CTRL
#endif  // #ifdef  SUPPORT_SCART_IF