hsystem.c

ct952 source code use for Digital Frame Photo

    // Disable external ADC
    REG_PLAT_SYSTEM_CONFIGURATION1 &= ~(1<<31);

    // Following procedure is used to calculate final system configuration1 value
    REG_PLAT_SYSTEM_CONFIGURATION1 = ( REG_PLAT_SYSTEM_CONFIGURATION1
    // LLY2.56, DMA arbiter control is necessary only for CT909R
#ifdef  CT909R_IC_SYSTEM
    // Set bit[10] as 1, just for CT909BB IC (DMA arbiter Control Register)
                                        + (0x1 << 10)
#endif  // #ifdef CT909R_IC_SYSTEM

    // LLY2.51, it's un-necessary to config system configuration 1 for external Audio DAC @ CT909P
    // Since, it was removed to GPE Mux selection register.
#ifdef CT909R_IC_SYSTEM
#if (AUDIO_DAC != DAC_INTERNAL)
#ifdef  SUPPORT_2_CHANNEL_ONLY
    // LLY2.20, only enable bit[24] for PCMSD0 while using external auido DAC + 2 channel only
                                        + (0x1<<24)
#else   // #ifdef SUPPORT_2_CHANNEL_ONLY
    // LLY2.20, enable bit[24, 25, 26, 27] for PCMSD0/1/2 while 5.1 channel solution.
                                        + (0xf<<24)
#endif  // #ifdef   SUPPORT_CHANNEL_ONLY
#endif  // #if (AUDIO_DAC != DAC_INTERNAL)
#endif  // #ifdef CT909R_IC_SYSTEM

    // LLY2.56, 2 channel only configuration is different @ CT909G
#ifdef CT909G_IC_SYSTEM
#if (AUDIO_DAC != DAC_INTERNAL)
#ifdef  SUPPORT_2_CHANNEL_ONLY
    // enable bit[25]: 5.1ch L/R and bit[24]: DAC aclk/ bclk/ ws while using external auido DAC + 2 channel only
                                        + (0x3<<24)
#else   // #ifdef SUPPORT_2_CHANNEL_ONLY
    // enable bit[27:25]: 5.1 ch and bit[24]: DAC aclk/ bclk/ ws while 5.1 channel solution.
                                        + (0xf<<24)
#endif  // #ifdef   SUPPORT_CHANNEL_ONLY
#endif  // #if (AUDIO_DAC != DAC_INTERNAL)
#endif  // #ifdef CT909G_IC_SYSTEM


#ifdef  SUPPORT_CCIR656
    // CCIR656: Set DVI[22]=1
    // CCIR601: Set DVI[22]=1 and SyncOut[23]=1
                                        + (1<<22)
// Alan2.18, Invert Pixel Clock, if not define "not to inverse VCLK" (default is off)
#ifndef VCLK_NO_INVERSE
                                        + (1<<21)
#endif  // #ifndef VCLK_NO_INVERSE
#endif  // #ifdef SUPPORT_CCIR656
                                        );

    MACRO_PLAT_KEY_UNLOCK( );
    OS_RESTORE_INTERRUPTS( dwSaveInt );

    // LLY2.51, must configuration GPE Mux selection register for external audio DAC @ CT909P
#ifdef  CT909P_IC_SYSTEM
#if (AUDIO_DAC != DAC_INTERNAL)
    // Always enable GPEMux[2:1] as 1 to enable PCMWS/ PCMCLK/ ACLK for external audio DAC
    REG_PLAT_GPE_MUX |= (0x3L<<1);
#ifdef  SUPPORT_2_CHANNEL_ONLY
    // Enable GPEMux[6]=1 to enable PCMSD0 for 2 channel only
    REG_PLAT_GPE_MUX |= (0x1L<<6);
#else   // #ifdef  SUPPORT_2_CHANNEL_ONLY
    // Enable GPEMux[6:3]=1 to enable PCMSD0/1/2/3 for 5.1 channel
    REG_PLAT_GPE_MUX |= (0xfL<<3);
#endif  // #ifdef  SUPPORT_2_CHANNEL_ONLY
#endif  // #if (AUDIO_DAC != DAC_INTERNAL)

#endif  // #ifdef CT909P_IC_SYSTEM

    // LLY2.16, remove the procedure to HAL_StartSystem(), since servo init may use expand GPIO
#if 0
    // LLY2.13, initial expand GPIO while using it
    // Notice: must put the procedure as earily as possible since servo init may use expand GPIO
    HAL_Init_ExpGPIO();
#endif  // #if 0

    // LLY2.38, remove DVD/ DVB switching procedure as earily as possible
    // ie. must earier than servo init.
    // Otherwise, servo action can't work.
    // LLY2.15, set DVD/ DVB switch mode as DVD while power-on
    // Otherwise, servo signal can't come-in
#if 0
#if (DECODER_SYSTEM != DVD909S_EVAL)
    HAL_WriteGPIO(DVD_DVB_SWITCH_GRP, PIN_DVD_DVB_SWITCH, 1);
#endif  // #if (DECODER_SYSTEM != DVD909S_EVAL)
#endif  // #if 0

#endif // #ifndef AP_FRAMEWORK

    // Initial OSD FIFO threshold @ REG_MCU_VCR24
    // And, multiple 2 for CT909S
    // LLY2.10-1, Chuan says 0x2004005 will cause previous video flash while DivX do pre-scan period
    // LLY2.12, porting Chuan's code to modify MCR4/ VCR24/ SYS_CONFIG1 for CT909S BB version IC
    // To fix OSD flick issue.
#if 0
    REG_MCU_MCR4 = 0x2004004; //0x2004005;  // DMA Arbiter Control Register
    REG_MCU_VCR24 = 0x3A20;
#endif  // #if 0
    // LLY2.56, DMA arbiter control is necessary only for CT909R
#ifdef  CT909R_IC_SYSTEM
    REG_MCU_MCR4 = 0x2002005;  // DMA Arbiter Control Register
#endif  // #ifdef CT909R_IC_SYSTEM
    REG_MCU_VCR24 = 0x3A20;

    // LLY1.21-1, remove code protection procedure before PROC2 go.
    INT_Init( );

    // LLY2.15, porting YC's code to enable watch-dog
    HAL_WatchDog_Enable(TRUE);


    if (dwAck)
    {
        return FALSE;
    }
    else
    {
        return TRUE;
    }

#endif  // #ifdef SYSTEM_ECOS
}


void HAL_PowerControl(BYTE bDevice, BYTE bAction)
{
    DWORD dwSaveInt;
    switch(bDevice)
    {
        // LLY2.36, add new case to power down PROC2, Not Test !!
        case    HAL_POWER_PROC2:
            if (bAction == HAL_POWER_NORMAL)
            {
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL &= ~(PLAT_MCLK_PROC2_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
                // Notice: delay a while to wait PROC2 enable ok
                OS_DelayTime(COUNT_50_MSEC);
            }
            else
            if (bAction == HAL_POWER_SAVE)
            {
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL |= (PLAT_MCLK_PROC2_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );

            }
            break;

        // LLY2.36, must control VDEC2 too
        case    HAL_POWER_VDEC:
            if (bAction == HAL_POWER_NORMAL)
            {
                if (REG_PLAT_CLK_GENERATOR_CONTROL & (PLAT_MCLK_VDEC_DISABLE|PLAT_MCLK2_VDEC_DISABLE))
                {
                    OS_DISABLE_INTERRUPTS( dwSaveInt );
                    REG_PLAT_CLK_GENERATOR_CONTROL &= ~(PLAT_MCLK_VDEC_DISABLE | PLAT_MCLK2_VDEC_DISABLE);
                    OS_RESTORE_INTERRUPTS( dwSaveInt );
                    // Notice: delay a while to wait VDEC enable ok
                    OS_DelayTime(COUNT_50_MSEC);
                }
            }
            else if (bAction == HAL_POWER_SAVE)
            {
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL |= (PLAT_MCLK_VDEC_DISABLE | PLAT_MCLK2_VDEC_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
            }
            break;

        case    HAL_POWER_PROM:
            if (bAction == HAL_POWER_NORMAL)
            {
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL &= ~(PLAT_MCLK_PROM_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
                // Notice: delay a while to wait PROM enable ok
                OS_DelayTime(COUNT_50_MSEC);
            }
            else
            if (bAction == HAL_POWER_SAVE)
            {
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL |= (PLAT_MCLK_PROM_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
            }
            break;

// LLY2.56, don't support USB path for CT909G
// Notice: using ifndef CT909G IC to instead of USB source temporally
//         since compiler error if disable "SUPPORT_USB_SOURCE"
//#ifdef  SUPPORT_USB_SOURCE
#ifndef CT909G_IC_SYSTEM
#ifdef SUPPORT_USB
        case    HAL_POWER_USB:
            if (bAction == HAL_POWER_NORMAL)
            {
#ifdef SUPPORT_USB_POWER_BY_IO
                if (SrcFilter_GetOTGMode() == USB_MODE_HOST)
                    HAL_WriteGPIO(USB_POWER_GRP, PIN_USB_POWER, 1); //Jeff 20050602 Add for USB_POWER
#endif
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL &= ~(PLAT_UCLK48M_USB_DISABLE | PLAT_HCLK_USB_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
                OS_DelayTime(COUNT_50_MSEC);
            }
            else if (bAction == HAL_POWER_SAVE)
            {

#ifdef SUPPORT_USB_POWER_BY_IO
                HAL_WriteGPIO(USB_POWER_GRP, PIN_USB_POWER, 0); //Jeff 20050602 Add for USB_POWER
#endif //
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                // wyc2.05-909S, update the code to enable USB clock and exit USB HW when entering DVD mode, also enable USB when
                // enter USB mode. This can avoid the USB HW to affect other modules.
                REG_PLAT_CLK_GENERATOR_CONTROL |= (PLAT_UCLK48M_USB_DISABLE | PLAT_HCLK_USB_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
                OS_DelayTime(COUNT_50_MSEC);
            }
            break;
#endif //
#endif  // #ifdef SUPPORT_STB

        // LLY2.13, add the procedure to power down all available MPEG part
        // LLY2.15, remove UART related setting.
        case    HAL_POWER_PLL:
            OS_DISABLE_INTERRUPTS( dwSaveInt );

            if (bAction == HAL_POWER_NORMAL)
            {
                // Now, 909S wake up procedure are:
                // (1) Power on MPLL/ APLL/ UPLL
                // (2) Set MCLK to select MPLL
                // (3) Readjust system time & UART baudrate since MCLK is updated.

                // LLY2.22, give CPU_SPEED directly
                // LLY2.36, do nothing while current MPLL clock is same as user desired
                if(__dwSysClk != CPU_SPEED)
                {
                    // LLY2.56, porting Chuan's code for CT909P/ CT909G power down control
                    // Since, they are different than CT909R
#ifdef  CT909R_IC_SYSTEM
                    // Restore all PLL as previous, bit[20]=0
                    REG_PLAT_MPLL_CONTROL &= ~(1 << 20);
                    REG_PLAT_APLL_CONTROL &= ~(1<< 20);
                    REG_PLAT_UPLL_CONTROL &= ~(1<< 20);
#else   // #ifdef CT909R_IC_SYSTEM
                    REG_PLAT_MPLL_CONTROL &= ~(1 << 8); // Power down MPLL/APLL/UPLL at the same time.
#endif  // #ifdef CT909R_IC_SYSTEM
                    HAL_ClockSet(MODE_MPLL, CPU_SPEED);
#ifdef EMU_RTC   
                    //Aron2.77, added for DMP SW-RTC
                    RTC_Emu_ChkTimerReload(RTC_EMU_WAKEUP);
#endif                
                }


                // Re-adjust system timer w/ normal system clock
                // Notice: must update the __dwSysClk value together
                __dwSysClk=CPU_SPEED;
                REG_PLAT_PRESCALER_RELOAD = ((__dwSysClk/1000000)-1)/2;

                // LLY2.15, reset baud rate for DSU1/ UART1/ UART2
                // Notice: need double how to reset DSU1 baudrate, since can't work
                //HAL_DSU_BaudRateSet((__dwSysClk/2), BAUDRATE_115200, HAL_DSU1);
                HAL_UART_BaudRateSet((__dwSysClk/2), BAUDRATE_115200, HAL_UART1);
                HAL_UART_BaudRateSet((__dwSysClk/2), BAUDRATE_115200, HAL_UART2);

            }
            else if(bAction == HAL_POWER_SAVE)
            {
                // Now, 909S power down method are:
                // (1) Set MCLK to select extra OSCI (27MHz)
                // (2) Power down MPLL/ APLL/ UPLL
                // (3) Readjust system time & UART baudrate since MCLK is updated.

                // LLY2.16, system clock must be work >= 54MHz
                // Otherwise, we will miss IR interrupt
                // IR work @ 27MHz, interrupt work @ pclk = system clock/2, and must >= 27MHz
                // LLY2.36, set power down CPU speed as 27M for power consumption issue
                // So, must change IR working mode from interrupt to polling @ 27M
                // LLY2.38, using global define to set desired CPU speed for power down mode.
                //if(HAL_ClockSet(MODE_MPLL, CPU_27M))
                if(HAL_ClockSet(MODE_MPLL, POWERDOWN_CPU_SPEED))
                {
                    // update the corresponding __dwSysClk value
                    //__dwSysClk=CPU_27M;
                    __dwSysClk=POWERDOWN_CPU_SPEED;

                    // Power down all PLL, bit[20]=1 while set as 27M
                    if(__dwSysClk==CPU_27M)
                    {
                    // LLY2.56, porting Chuan's code for CT909P/ CT909G power down control
                    // Since, they are different than CT909R
#ifdef  CT909R_IC_SYSTEM
                        REG_PLAT_MPLL_CONTROL |= (1 << 20);
                        REG_PLAT_APLL_CONTROL |= (1<< 20);
                        REG_PLAT_UPLL_CONTROL |= (1<< 20);
#else   // #ifdef CT909R_IC_SYSTEM
                        REG_PLAT_MPLL_CONTROL |= (1 << 8);
#endif  // #ifdef CT909R_IC_SYSTEM
#ifdef EMU_RTC
                        //Aron2.77, added for DMP SW-RTC
                        RTC_Emu_ChkTimerReload(RTC_EMU_SLEEP);
#endif
                    }
                }
                else
                {
                    // LLY2.36, must restore the original MPLL clock
                    // Since user desired setting is not work
                    __dwSysClk=CPU_SPEED;
                }


                // Re-adjust system timer w/ new system clock
                REG_PLAT_PRESCALER_RELOAD = ((__dwSysClk/1000000)-1)/2;

                // LLY2.15, reset baud rate for DSU1/ UART1/ UART2
                // Notice: need double how to reset DSU1 baudrate, since can't work
                //HAL_DSU_BaudRateSet((__dwSysClk/2), BAUDRATE_115200, HAL_DSU1);
                HAL_UART_BaudRateSet((__dwSysClk/2), BAUDRATE_115200, HAL_UART1);
                HAL_UART_BaudRateSet((__dwSysClk/2), BAUDRATE_115200, HAL_UART2);

            }

            OS_RESTORE_INTERRUPTS( dwSaveInt );
            break;

#ifndef  SUPPORT_SERVO_SOURCE
        case    HAL_POWER_SERVO:
            if (bAction == HAL_POWER_NORMAL)
            {
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL &= ~(PLAT_CDCLK_DISABLE | PLAT_DVDCLK_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
                OS_DelayTime(COUNT_50_MSEC);
            }
            else
            if (bAction == HAL_POWER_SAVE)
            {
                // (*(volatile DWORD *)(0x800026F8) = (DWORD)(1<<20); // Power down ADC6
                // MACRO_IDLE();
                OS_DISABLE_INTERRUPTS( dwSaveInt );
                REG_PLAT_CLK_GENERATOR_CONTROL |= (PLAT_CDCLK_DISABLE | PLAT_DVDCLK_DISABLE);
                OS_RESTORE_INTERRUPTS( dwSaveInt );
            }
            break;
#endif	// #ifndef  SUPPORT_SERVO_SOURCE

        default:
                break;

    }
}

//**************************************************************************
// Description  :   Use an IO pin to act as H/W circuit mute in parallel with P_MUTE/D_MUTE
// Arguments    :   bMute: TRUE: mute
//                           FALSE: unmute
// Return       :   None
//***************************************************************************
void    HAL_IOMute(BYTE bMute) //test OK
{
    // LLY2.11, disable UART2 while IOMUTE pin is shared w/ UART2
    // LLY2.15, don't disble UART2 here since programmer maybe use it for debug and skip IOMUTE
#if 0//def IOMUTE_UART2_SAME_PORT