📄 ctkav_mcu.h

📁 ct952 source code use for Digital Frame Photo
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#define REG_MCU_REMEN_ADDR  ((PDWORD) (REG_MCU_BASE+0x680))                 // Buffer Remainder Enable Register#define REG_MCU_VEDIO_REMCTL      (*((volatile DWORD *) (REG_MCU_BASE+0x684)))    // Vedio Buffer Remainder Control Register#define REG_MCU_VEDIO_REMCTL_ADDR ((PDWORD) (REG_MCU_BASE+0x684))                 // Vedio Buffer Remainder Control Register#define REG_MCU_AUDIO_REMCTL      (*((volatile DWORD *) (REG_MCU_BASE+0x688)))    // Audio Buffer Remainder Control Register#define REG_MCU_AUDIO_REMCTL_ADDR ((PDWORD) (REG_MCU_BASE+0x688))                 // Audio Buffer Remainder Control Register#define REG_MCU_A0REM       (*((volatile DWORD *) (REG_MCU_BASE+0x690)))    // Audio Bit-stream Buffer 0 Remainder#define REG_MCU_A0REM_ADDR  ((PDWORD) (REG_MCU_BASE+0x690))                 // Audio Bit-stream Buffer 0 Remainder#define REG_MCU_A0OTH       (*((volatile DWORD *) (REG_MCU_BASE+0x694)))    // Audio Bit-stream Buffer 0 Overflow Threshold#define REG_MCU_A0UTH       (*((volatile DWORD *) (REG_MCU_BASE+0x698)))    // Audio Bit-stream Buffer 0 Underflow Threshold#define REG_MCU_A1REM       (*((volatile DWORD *) (REG_MCU_BASE+0x6a0)))    // Audio Bit-stream Buffer 1 Remainder#define REG_MCU_A1REM_ADDR  ((PDWORD) (REG_MCU_BASE+0x6a0))                 // Audio Bit-stream Buffer 1 Remainder#define REG_MCU_A1OTH       (*((volatile DWORD *) (REG_MCU_BASE+0x6a4)))    // Audio Bit-stream Buffer 1 Overflow Threshold#define REG_MCU_A1UTH       (*((volatile DWORD *) (REG_MCU_BASE+0x6a8)))    // Audio Bit-stream Buffer 1 Underflow Threshold#define REG_MCU_AADD        (*((volatile DWORD *) (REG_MCU_BASE+0x6ac)))    // Audio Buffer 0 Addend/Subtrahend#define REG_MCU_VREM        (*((volatile DWORD *) (REG_MCU_BASE+0x6b0)))    // Video Bit-stream Buffer Remainder#define REG_MCU_VREM_ADDR   ((PDWORD) (REG_MCU_BASE+0x6b0))                 // Video Bit-stream Buffer Remainder#define REG_MCU_VOTH        (*((volatile DWORD *) (REG_MCU_BASE+0x6b4)))    // Video Bit-stream Buffer Overflow Threshold#define REG_MCU_VUTH        (*((volatile DWORD *) (REG_MCU_BASE+0x6b8)))    // Video Bit-stream Buffer Underflow Threshold#define REG_MCU_VADD        (*((volatile DWORD *) (REG_MCU_BASE+0x6bc)))    // Video Buffer 0 Addend/Subtrahend#define REG_MCU_SP1REM      (*((volatile DWORD *) (REG_MCU_BASE+0x6c0)))    // SP1 Bit-stream Buffer Remainder#define REG_MCU_SP1REM_ADDR ((PDWORD) (REG_MCU_BASE+0x6c0))                 // SP1 Bit-stream Buffer Remainder#define REG_MCU_SP1OTH      (*((volatile DWORD *) (REG_MCU_BASE+0x6c4)))    // SP1 Bit-stream Buffer Overflow Threshold#define REG_MCU_VSETVALUE      (*((volatile DWORD *) (REG_MCU_BASE+0x6c8)))    // Video bit-stream buffer initial setting value#define REG_MCU_SP1SUB      (*((volatile DWORD *) (REG_MCU_BASE+0x6cc)))    // SP1 Bit-stream Buffer Remainder Subtrahend#define REG_MCU_SP2REM      (*((volatile DWORD *) (REG_MCU_BASE+0x6d0)))    // SP2 Bit-stream Buffer Remainder#define REG_MCU_SP2REM_ADDR ((PDWORD) (REG_MCU_BASE+0x6d0))                 // SP2 Bit-stream Buffer Remainder#define REG_MCU_SP2OTH      (*((volatile DWORD *) (REG_MCU_BASE+0x6d4)))    // SP2 Bit-stream Buffer Overflow Threshold#define REG_MCU_SP2SUB      (*((volatile DWORD *) (REG_MCU_BASE+0x6dc)))    // SP2 Bit-stream Buffer Remainder Subtrahend#define REG_MCU_PCMREM      (*((volatile DWORD *) (REG_MCU_BASE+0x6e0)))    // PCM Buffer Remainder#define REG_MCU_PCMOTH      (*((volatile DWORD *) (REG_MCU_BASE+0x6e4)))    // PCM Buffer Overflow Threshold#define REG_MCU_PCMUTH      (*((volatile DWORD *) (REG_MCU_BASE+0x6e8)))    // PCM Buffer Underflow Threshold#define REG_MCU_SPDIFREM    (*((volatile DWORD *) (REG_MCU_BASE+0x6f0)))    // SPDIF Output Buffer Remainder#define REG_MCU_SPDIFOTH    (*((volatile DWORD *) (REG_MCU_BASE+0x6f4)))    // SPDIF Output Buffer Overflow Threshold#define REG_MCU_SPDIFUTH    (*((volatile DWORD *) (REG_MCU_BASE+0x6f8)))    // SPDIF Output Buffer Underflow Threshold#define REG_MCU_SPDIFADD    (*((volatile DWORD *) (REG_MCU_BASE+0x6fc)))    // SPDIF buffer addend/subtrahend#define REG_MCU_PCM0REM     (*((volatile DWORD *) (REG_MCU_BASE+0x700)))    // PCM Buffer 0 Remainder#define REG_MCU_PCM0OTH     (*((volatile DWORD *) (REG_MCU_BASE+0x704)))    // PCM Buffer 0 Overflow Threshold#define REG_MCU_PCM0UTH     (*((volatile DWORD *) (REG_MCU_BASE+0x708)))    // PCM Buffer 0 Underflow Threshold#define REG_MCU_PCM0ADD     (*((volatile DWORD *) (REG_MCU_BASE+0x70c)))    // PCM Buffer 0 Addend/Subtrahend#define REG_MCU_STBREM     (*((volatile DWORD *) (REG_MCU_BASE+0x710)))    // STB Buffer Remainder#define REG_MCU_STBOTH     (*((volatile DWORD *) (REG_MCU_BASE+0x714)))    // STB Buffer Overflow Threshold#define REG_MCU_STBUTH     (*((volatile DWORD *) (REG_MCU_BASE+0x718)))    // STB Buffer Underflow Threshold// define write protection is occurred by which module#define MCU_WRITE_PROTECT_STATUS_SI_WRITE                           (0x001)#define MCU_WRITE_PROTECT_STATUS_VPU_WRITE                          (0x002)#define MCU_WRITE_PROTECT_STATUS_MC_WRITE                           (0x004)#define MCU_WRITE_PROTECT_STATUS_READ_MODIFY_WRITE_CHANNEL_WRITE    (0x008)#define MCU_WRITE_PROTECT_STATUS_STB_WRITE                          (0x010)#define MCU_WRITE_PROTECT_STATUS_DUMP_IN_WRITE                      (0x020)#define MCU_WRITE_PROTECT_STATUS_BIU_WRITE                          (0x040)#define MCU_WRITE_PROTECT_STATUS_MIC2_WRITE                         (0x080)#define MCU_WRITE_PROTECT_STATUS_MIC_WRITE                          (0x100)#define MCU_WRITE_PROTECT_STATUS_AIU_WRITE                          (0x200)#define MCU_WRITE_PROTECT_STATUS_CLB_WRITE                          (0x400)#define MCU_WRITE_PROTECT_STATUS_AHB_WRITE                          (0x200)// define write protection area enable bit#define MCU_WRITE_PROTECT_AREA0_ENABLE              (0x00000001)#define MCU_WRITE_PROTECT_AREA1_ENABLE              (0x00000002)#define MCU_WRITE_PROTECT_AREA2_ENABLE              (0x00000004)#define MCU_WRITE_PROTECT_AREA3_ENABLE              (0x00000008)#define MCU_WRITE_PROTECT_AREA4_ENABLE              (0x00000010)#define MCU_WRITE_PROTECT_AREA5_ENABLE              (0x00000020)#define MCU_WRITE_PROTECTION_DISABLE_ALL            (0x00000000)#define MCU_WRITE_PROTECTION_ENABLE_ALL             (0x0000003f)// define bitstream type of REMCTL#define MCU_BIT_STREAM_TYPE_MASK                    (0x00000007)#define MCU_BIT_STREAM_TYPE_UNMASK                  (~MCU_BIT_STREAM_TYPE_MASK)#define MCU_BIT_STREAM_AUDIO                        (0x00000000)#define MCU_BIT_STREAM_VIDEO                        (0x00000001)#define MCU_BIT_STREAM_SP1                          (0x00000002)#define MCU_BIT_STREAM_SP2                          (0x00000003)#define MCU_BIT_STREAM_DATA                         (0x00000005)// define enable bit of REMEM#define MCU_REMAINDER_ENABLE_AUDIO_BUF0             (0x00000001)#define MCU_REMAINDER_ENABLE_AUDIO_BUF1             (0x00000002)#define MCU_REMAINDER_ENABLE_VIDEO_BUF              (0x00000004)#define MCU_REMAINDER_ENABLE_SP1_BUF                (0x00000008)#define MCU_REMAINDER_ENABLE_SP2_BUF                (0x00000010)#define MCU_REMAINDER_ENABLE_PCM_BUF                (0x00000020)#define MCU_REMAINDER_ENABLE_SPDIF_OUTPUT           (0x00000040)#define MCU_REMAINDER_ENABLE_PCM0_BUF               (0x00000080)#define MCU_REMAINDER_ENABLE_STB_BUF                (0x00000100)#define MCU_REMAINDER_ENABLE_ALL                    (0x000001ff)#define MCU_A0_REMAINDER_ADD                        (0x00000200)#define MCU_A0_REMAINDER_SUB                        (0x00000100)#define MCU_A1_REMAINDER_ADD                        (0x02000000)#define MCU_A1_REMAINDER_SUB                        (0x01000000)#define MCU_AADD_REMAINDER_ACRCSET                  (0x10000000) // acrcset : if set (1), the upk0_rdpt-18 => upk1_rdpt, abuf0rem-18 => abuf1rem#define MCU_SP_REMAINDER_SUB                        (0x00010000)#define MCU_REMAINDER_ADD                           (0x00000200)#define MCU_REMAINDER_SUB                           (0x00000100)#define MCU_REMAINDER_INIT                          (0x01000000)// define channel select of REMCTL#define MCU_AIU_CHANNEL_SELECT_MASK                 (0x00007f00)#define MCU_AIU_CHANNEL_SELECT_UNMASK               (~MCU_AIU_CHANNEL_SELECT_MASK)#define MCU_AIUWR_CHANNEL_SELECT_MASK               (0x00000300)#define MCU_AIUWR_CHANNEL_SELECT_UNMASK             (~MCU_AIUWR_CHANNEL_SELECT_MASK)#define MCU_AIUWR_CHANNEL_SELECT_PCM                (0x00000000)#define MCU_AIUWR_CHANNEL_SELECT_SPDIF_OUTPUT       (0x00000100)#define MCU_AIUWR_CHANNEL_SELECT_AUDIO              (0x00000200)#define MCU_AUDIO_BUF0_CHANNEL_SELECT_MASK          (0x00000c00)#define MCU_AUDIO_BUF0_CHANNEL_SELECT_UNMASK        (~MCU_AUDIO_BUF0_CHANNEL_SELECT_MASK)#define MCU_AUDIO_BUF0_CHANNEL_SELECT_BIUWR         (0x00000000)#define MCU_AUDIO_BUF0_CHANNEL_SELECT_SPDIF_IN      (0x00000400)#define MCU_AUDIO_BUF0_CHANNEL_SELECT_AIUWR         (0x00000800)#define MCU_AUDIO_BUF1_CHANNEL_SELECT_MASK          (0x00003000)#define MCU_AUDIO_BUF1_CHANNEL_SELECT_UNMASK        (~MCU_AUDIO_BUF0_CHANNEL_SELECT_MASK)#define MCU_AUDIO_BUF1_CHANNEL_SELECT_BIUWR         (0x00000000)#define MCU_AUDIO_BUF1_CHANNEL_SELECT_AIUWR         (0x00002000)#define MCU_UNPACKER1_CHANNEL_SELECT_MASK           (0x00004000)#define MCU_UNPACKER1_CHANNEL_SELECT_UNMASK         (~MCU_UNPACKER1_CHANNEL_SELECT_MASK)#define MCU_UNPACKER1_CHANNEL_SELECT_AUDIO_BUF1     (0x00000000)#define MCU_UNPACKER1_CHANNEL_SELECT_PCM0           (0x00004000)#define MCU_MASK_BIU_BIT_STREAM_FIFO_REMAINDER      (0x00000000)#define MCU_MASK_BIU_WRITE_CHANNEL_FIFO_REMAINDER   (0x000f0000)#define MCU_SHIFT_BIU_WRITE_CHANNEL_FIFO_REMAINDER  (16)#define MCU_BIU_WRITE_CHANNEL_FIFO_REMAINDER        (REG_MCU_BCR04 >> 16)// DMA FIFO channel FIFO clear Register (MCU_MCR5)#define MCU_RESET_AIU_MIC_WRITE_FIFO                (0x00000001)#define MCU_RESET_STB_WRITE_FIFO                    (0x00000400)#define MCU_RESET_AIU_MIC2_WRITE_FIFO               (0x04000000)#define MCU_RESET_AIU_UPK0_FIFO                     (0x00000002)#define MCU_RESET_AIU_UPK1_FIFO                     (0x00000004)#define MCU_RESET_AIU_PCM_READ_FIFO                 (0x00000008)#define MCU_RESET_AIU_SPDIF_READ_FIFO               (0x00000010)#define MCU_RESET_AIU_WRITE_FIFO                    (0x00000020)#define MCU_RESET_AIU_READ_FIFO                     (0x00000040)#define MCU_RESET_BIU_WRITE_FIFO                    (0x00000100)#define MCU_RESET_BIU_READ_FIFO                     (0x00000200)#define MCU_RESET_VDEC_READ_FIFO                    (0x00001000)#define MCU_RESET_SP_TOP_FIFO                       (0x00010000)#define MCU_RESET_SP_BOTTOM_FIFO                    (0x00020000)#define MCU_RESET_SP_COLOR_FIFO                     (0x00040000)#define MCU_RESET_TELETEXT_FIFO                     (0x00080000)#define MCU_RESET_OSD_READ_FIFO                     (0x00100000)#define MCU_RESET_SERVO_EDC_FIFO                    (0x01000000)#define MCU_RESET_SERVO_ECC_FIFO                    (0x02000000)// BIU Bit-Stream Format (MCU_BCR0D)#define MCU_BSTYPE_DVD                              (0x00000000)#define MCU_BSTYPE_CD                               (0x40000000)#define MCU_BSTYPE_ATAPI                            (0x80000000)// define interrupt enable bit of MCU_MCR6 Interrupt Control Register 1#define MCU_INTCTL1_AUDIO_BUF0_OVERFLOW_ENABLE      (0x00000001)#define MCU_INTCTL1_AUDIO_BUF1_OVERFLOW_ENABLE      (0x00000002)#define MCU_INTCTL1_BIUBR_CHANNEL_DONE_ENABLE       (0x00000004)#define MCU_INTCTL1_BIUBR_FIFO_FULL_ENABLE          (0x00000008)#define MCU_INTCTL1_AUDIO_BUF0_OVERFLOW_STATUS      (0x00000010)#define MCU_INTCTL1_AUDIO_BUF1_OVERFLOW_STATUS      (0x00000020)#define MCU_INTCTL1_AUDIO_BUF_STATUS_UPDATE         (0x00000040)#define MCU_INTCTL1_BIUBR_CHANNEL_DONE_STATUS       (0x00000080)#define MCU_INTCTL1_BIUBR_FIFO_FULL_STATUS          (0x00000100)#define MCU_INTCTL1_BIUBR_STATUS_UPDATE             (0x00000200)#define MCU_INTCTL1_BIUBR_STATUS_MASK               (MCU_INTCTL1_BIUBR_FIFO_FULL_STATUS|MCU_INTCTL1_BIUBR_CHANNEL_DONE_STATUS)#define MCU_INTCTL1_AUDIO_STATUS_MASK               (MCU_INTCTL1_AUDIO_BUF0_OVERFLOW_STATUS|MCU_INTCTL1_AUDIO_BUF1_OVERFLOW_STATUS)// define interrupt enable bit of MCU_MCR7 Interrupt Control Register 2#define MCU_INTCTL2_AUDIO_BUF0_UNDERFLOW_ENABLE     (0x00000001)
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