ctkav_mcu.h

ct952 source code use for Digital Frame Photo

#ifndef __CTKAV_MCU_H__
#define __CTKAV_MCU_H__

#ifdef __cplusplus
extern "C" {
#endif //__cplusplus

#define REG_MCU_BASE        (CT909_IO_START+0x880)

#define REG_MCU_MR0         (*((volatile DWORD *) (REG_MCU_BASE+0x000)))    // MCU Configuration Register
#define REG_MCU_MCR1        (*((volatile DWORD *) (REG_MCU_BASE+0x004)))    // SDRAM Base Address
#define REG_MCU_MCR2        (*((volatile DWORD *) (REG_MCU_BASE+0x008)))    // SDRAM AC Timing Setting
#define REG_MCU_MCR3        (*((volatile DWORD *) (REG_MCU_BASE+0x00c)))    // DMA Refresh/Initialization Register
#define REG_MCU_MCR4        (*((volatile DWORD *) (REG_MCU_BASE+0x010)))    // DMA Arbiter Control Register
#define REG_MCU_MCR5        (*((volatile DWORD *) (REG_MCU_BASE+0x014)))    // DMA channel FIFO clear Register
                                                                            // D13 BIU Read, D12 BIU Write
#define REG_MCU_MCR6        (*((volatile DWORD *) (REG_MCU_BASE+0x018)))    // Interrupt Control Register 1
#define REG_MCU_MCR7        (*((volatile DWORD *) (REG_MCU_BASE+0x01c)))    // Interrupt Control Register 2
#define REG_MCU_CCR00       (*((volatile DWORD *) (REG_MCU_BASE+0x020)))    // Clean Buffer Write Channel Base Address
#define REG_MCU_CCR01       (*((volatile DWORD *) (REG_MCU_BASE+0x024)))    // Clean Buffer Fill Data and Byte Number

#define REG_MCU_ACR40       (*((volatile DWORD *) (REG_MCU_BASE+0x060)))    // AIU MIC2 Write Channel Base Address
#define REG_MCU_ACR41       (*((volatile DWORD *) (REG_MCU_BASE+0x064)))    // AIU MIC2 Write Channel Write Address
#define REG_MCU_ACR42       (*((volatile DWORD *) (REG_MCU_BASE+0x068)))    // AIU MIC2 Write Address Upper Boundary
#define REG_MCU_ACR43       (*((volatile DWORD *) (REG_MCU_BASE+0x06c)))    // AIU MIC2 Write Address Lower Boundary
#define REG_MCU_ACR44       (*((volatile DWORD *) (REG_MCU_BASE+0x070)))    // AIU MIC2 Write Channel FIFO Status

#define REG_MCU_ACR00       (*((volatile DWORD *) (REG_MCU_BASE+0x080)))    // AIU SPDIF Write Channel Base Address of SPDIF_BUF 1
#define REG_MCU_ACR01       (*((volatile DWORD *) (REG_MCU_BASE+0x084)))    // AIU SPDIF Write Channel Write Address
#define REG_MCU_ACR02       (*((volatile DWORD *) (REG_MCU_BASE+0x088)))    // AIU SPDIF Write Address Upper Boundary of SPDIF_BUF 1
#define REG_MCU_ACR03       (*((volatile DWORD *) (REG_MCU_BASE+0x08c)))    // AIU SPDIF Write Address Lower Boundary of SPDIF_BUF 1
#define REG_MCU_ACR04       (*((volatile DWORD *) (REG_MCU_BASE+0x090)))    // AIU SPDIF Write Channel FIFO Status Register

#define REG_MCU_ACR08       (*((volatile DWORD *) (REG_MCU_BASE+0x0a0)))    // AIU Unpacker0 Read Channel Base Address
#define REG_MCU_ACR09       (*((volatile DWORD *) (REG_MCU_BASE+0x0a4)))    // AIU Unpacker0 Read Channel Read Address
#define REG_MCU_ACR0A       (*((volatile DWORD *) (REG_MCU_BASE+0x0a8)))    // AIU Unpacker0 Read Address Upper Boundary
#define REG_MCU_ACR0B       (*((volatile DWORD *) (REG_MCU_BASE+0x0ac)))    // AIU Unpacker0 Read Address Lower Boundary
#define REG_MCU_ACR0C       (*((volatile DWORD *) (REG_MCU_BASE+0x0b0)))    // AIU Unpacker0 Read Channel FIFO Status Register
#define REG_MCU_ACR10       (*((volatile DWORD *) (REG_MCU_BASE+0x0c0)))    // AIU Unpacker1 Read Channel Base Address
#define REG_MCU_ACR11       (*((volatile DWORD *) (REG_MCU_BASE+0x0c4)))    // AIU Unpacker1 Read Channel Read Address
#define REG_MCU_ACR12       (*((volatile DWORD *) (REG_MCU_BASE+0x0c8)))    // AIU Unpacker1 Read Address Upper Boundary
#define REG_MCU_ACR13       (*((volatile DWORD *) (REG_MCU_BASE+0x0cc)))    // AIU Unpacker1 Read Address Lower Boundary
#define REG_MCU_ACR14       (*((volatile DWORD *) (REG_MCU_BASE+0x0d0)))    // AIU Unpacker1 Read Channel FIFO Status Register
#define REG_MCU_ACR18       (*((volatile DWORD *) (REG_MCU_BASE+0x0e0)))    // AIU PCM Read Channel Base Address
#define REG_MCU_ACR19       (*((volatile DWORD *) (REG_MCU_BASE+0x0e4)))    // AIU PCM Read Channel Read Address
#define REG_MCU_ACR1A       (*((volatile DWORD *) (REG_MCU_BASE+0x0e8)))    // AIU PCM Read Address Upper Boundary
#define REG_MCU_ACR1B       (*((volatile DWORD *) (REG_MCU_BASE+0x0ec)))    // AIU PCM Read Address Lower Boundary
#define REG_MCU_ACR1C       (*((volatile DWORD *) (REG_MCU_BASE+0x0f0)))    // AIU PCM Read Channel FIFO Status Register
#define REG_MCU_ACR20       (*((volatile DWORD *) (REG_MCU_BASE+0x100)))    // AIU SPDIF Read Channel Base Address
#define REG_MCU_ACR21       (*((volatile DWORD *) (REG_MCU_BASE+0x104)))    // AIU SPDIF Read Channel Read Address
#define REG_MCU_ACR22       (*((volatile DWORD *) (REG_MCU_BASE+0x108)))    // AIU SPDIF Read Address Upper Boundary
#define REG_MCU_ACR23       (*((volatile DWORD *) (REG_MCU_BASE+0x10c)))    // AIU SPDIF Read Address Lower Boundary
#define REG_MCU_ACR24       (*((volatile DWORD *) (REG_MCU_BASE+0x110)))    // AIU SPDIF Read Channel FIFO Status Register
#define REG_MCU_ACR28       (*((volatile DWORD *) (REG_MCU_BASE+0x120)))    // AIU Write Channel Base Address
#define REG_MCU_ACR29       (*((volatile DWORD *) (REG_MCU_BASE+0x124)))    // AIU Write Channel Write Address
#define REG_MCU_ACR2A       (*((volatile DWORD *) (REG_MCU_BASE+0x128)))    // AIU Write Address Upper Boundary
#define REG_MCU_ACR2B       (*((volatile DWORD *) (REG_MCU_BASE+0x12c)))    // AIU Write Address Lower Boundary
#define REG_MCU_ACR2C       (*((volatile DWORD *) (REG_MCU_BASE+0x130)))    // AIU Write Channel FIFO Status Register
#define REG_MCU_ACR30       (*((volatile DWORD *) (REG_MCU_BASE+0x140)))    // AIU Read Channel Base Address
#define REG_MCU_ACR31       (*((volatile DWORD *) (REG_MCU_BASE+0x144)))    // AIU Read Channel Read Address
#define REG_MCU_ACR32       (*((volatile DWORD *) (REG_MCU_BASE+0x148)))    // AIU Read Address Upper Boundary
#define REG_MCU_ACR33       (*((volatile DWORD *) (REG_MCU_BASE+0x14c)))    // AIU Read Address Lower Boundary
#define REG_MCU_ACR34       (*((volatile DWORD *) (REG_MCU_BASE+0x150)))    // AIU Read Channel FIFO Status Register

#define REG_MCU_ACR35       (*((volatile DWORD *) (REG_MCU_BASE+0x154)))    // AIU Read Channel x, y direction increment
#define REG_MCU_ACR36       (*((volatile DWORD *) (REG_MCU_BASE+0x160)))    // AIU MIC Read Channel Base Address
#define REG_MCU_ACR37       (*((volatile DWORD *) (REG_MCU_BASE+0x164)))    // AIU MIC Read Channel current Read Address
#define REG_MCU_ACR38       (*((volatile DWORD *) (REG_MCU_BASE+0x168)))    // AIU MIC Read Address Upper Boundary
#define REG_MCU_ACR39       (*((volatile DWORD *) (REG_MCU_BASE+0x16c)))    // AIU MIC Read Address Lower Boundary
#define REG_MCU_ACR3A       (*((volatile DWORD *) (REG_MCU_BASE+0x170)))    // AIU MIC Read Channel FIFO Status
#define REG_MCU_ACR3B       (*((volatile DWORD *) (REG_MCU_BASE+0x174)))    // AIU MIC Read Channel read address offset

// BIU write channel
#define REG_MCU_BCR00       (*((volatile DWORD *) (REG_MCU_BASE+0x180)))    // BIU write channel base address
#define REG_MCU_BCR00_ADDR  ((PDWORD) (REG_MCU_BASE+0x180))                 // BIU write channel base address
#define REG_MCU_BCR01       (*((volatile DWORD *) (REG_MCU_BASE+0x184)))    // BIU write channel current write address
#define REG_MCU_BCR01_ADDR  ((PDWORD) (REG_MCU_BASE+0x184))                 // BIU write channel current write address
#define REG_MCU_BCR02       (*((volatile DWORD *) (REG_MCU_BASE+0x188)))    // BIU write channel upper boundary
#define REG_MCU_BCR03       (*((volatile DWORD *) (REG_MCU_BASE+0x18c)))    // BIU write channel lower boundary
#define REG_MCU_BCR04       (*((volatile DWORD *) (REG_MCU_BASE+0x190)))    // BIU write channel FIFO status


// BIU bit stream read channel for ATAPI (linear buffer)
#define REG_MCU_BCR08       (*((volatile DWORD *) (REG_MCU_BASE+0x1a0)))    // BIU bit stream read channel base address
#define REG_MCU_BCR08_ADDR  ((PDWORD) (REG_MCU_BASE+0x1a0))                 // BIU bit stream read channel base address
#define REG_MCU_BCR09       (*((volatile DWORD *) (REG_MCU_BASE+0x1a4)))    // BIU bit stream read channel current read address
#define REG_MCU_BCR09_ADDR  ((PDWORD) (REG_MCU_BASE+0x1a4))                 // BIU bit stream read channel current read address
#define REG_MCU_BCR0A       (*((volatile DWORD *) (REG_MCU_BASE+0x1a8)))    // BIU bit stream read channel x, y direction increment
#define REG_MCU_BCR0B       (*((volatile DWORD *) (REG_MCU_BASE+0x1ac)))    // BIU bit stream read channel x, y direction sub-increment
// remainder is at [19:16], range from 0 to 15
#define REG_MCU_BCR0C       (*((volatile DWORD *) (REG_MCU_BASE+0x1b0)))    // BIU bit stream read channel FIFO status
#define REG_MCU_BCR0D       (*((volatile DWORD *) (REG_MCU_BASE+0x1b4)))    // [31:30] bsrdtype "10", [23:16] bsrdheight "1",
                                                                            // [9:0] bsrdwidth (i.e. # of 64-bit)
#define REG_MCU_BCR0D_ADDR  ((PDWORD) (REG_MCU_BASE+0x1b4))                 // [31:30] bsrdtype "10", [23:16] bsrdheight "1",
#define REG_MCU_BCR0E       (*((volatile DWORD *) (REG_MCU_BASE+0x1b8)))    // BIU Bit-Stream Read Channel Sub-Block Width/Height

#define REG_MCU_SW_TRIGGER  (*((volatile DWORD *) (REG_MCU_BASE+0x1bc)))    // trigger DMA starting

#define REG_MCU_BCR10       (*((volatile DWORD *) (REG_MCU_BASE+0x1c0)))    // ATAPI Write Channel Base Address
#define REG_MCU_BCR11       (*((volatile DWORD *) (REG_MCU_BASE+0x1c4)))    // ATAPI Write Channel Write Address
#define REG_MCU_BCR12       (*((volatile DWORD *) (REG_MCU_BASE+0x1c8)))    // ATAPI Write Channel Write Count
#define REG_MCU_BCR13       (*((volatile DWORD *) (REG_MCU_BASE+0x1cc)))    // ATAPI Write Channel X Direction Increment
#define REG_MCU_BCR14       (*((volatile DWORD *) (REG_MCU_BASE+0x1d0)))    // ATAPI Write Channel FIFO Status Register

#define REG_MCU_DCR00       (*((volatile DWORD *) (REG_MCU_BASE+0x380)))    // VDEC VLD Read Channel Base Address
#define REG_MCU_DCR01       (*((volatile DWORD *) (REG_MCU_BASE+0x384)))    // VDEC VLD Read Channel Read Address
#define REG_MCU_DCR02       (*((volatile DWORD *) (REG_MCU_BASE+0x388)))    // VDEC VLD Read Channel upper boundary
#define REG_MCU_DCR03       (*((volatile DWORD *) (REG_MCU_BASE+0x38c)))    // VDEC VLD Read Channel lower boundary
#define REG_MCU_DCR04       (*((volatile DWORD *) (REG_MCU_BASE+0x390)))    // VDEC VLD Read Channel FIFO Status

#define REG_MCU_VCR00       (*((volatile DWORD *) (REG_MCU_BASE+0x480)))    // VOU SP Top Read Channel Base Address of SP1
#define REG_MCU_VCR01       (*((volatile DWORD *) (REG_MCU_BASE+0x484)))    // VOU SP Top Read Channel Read Address
#define REG_MCU_VCR02       (*((volatile DWORD *) (REG_MCU_BASE+0x488)))    // VOU SP Read Address Upper Boundary of SP1
#define REG_MCU_VCR03       (*((volatile DWORD *) (REG_MCU_BASE+0x48c)))    // VOU SP Read Address Lower Boundary of SP1
#define REG_MCU_VCR04       (*((volatile DWORD *) (REG_MCU_BASE+0x490)))    // VOU SP Top Read Channel FIFO Status Register
#define REG_MCU_VCR05       (*((volatile DWORD *) (REG_MCU_BASE+0x494)))    // VOU SP Top Read Channel Base Address of SP2
#define REG_MCU_VCR06       (*((volatile DWORD *) (REG_MCU_BASE+0x498)))    // VOU SP Read Address Upper Boundary of SP2
#define REG_MCU_VCR07       (*((volatile DWORD *) (REG_MCU_BASE+0x49c)))    // VOU SP Read Address Lower Boundary of SP2
#define REG_MCU_VCR08       (*((volatile DWORD *) (REG_MCU_BASE+0x4a0)))    // VOU SP Bottom Read Channel Base Address of SP1
#define REG_MCU_VCR09       (*((volatile DWORD *) (REG_MCU_BASE+0x4a4)))    // VOU SP Bottom Read Channel Read Address
#define REG_MCU_VCR0C       (*((volatile DWORD *) (REG_MCU_BASE+0x4b0)))    // VOU SP Bottom Read Channel FIFO Status Register
#define REG_MCU_VCR0D       (*((volatile DWORD *) (REG_MCU_BASE+0x4b4)))    // VOU SP Bottom Read Channel Base Address of SP2
#define REG_MCU_VCR10       (*((volatile DWORD *) (REG_MCU_BASE+0x4c0)))    // VOU SP Color Data Read Channel Base Address of SP1
#define REG_MCU_VCR11       (*((volatile DWORD *) (REG_MCU_BASE+0x4c4)))    // VOU SP Color Data Read Channel Read Address
#define REG_MCU_VCR14       (*((volatile DWORD *) (REG_MCU_BASE+0x4d0)))    // VOU SP Color Data Read Channel FIFO Status Register
#define REG_MCU_VCR15       (*((volatile DWORD *) (REG_MCU_BASE+0x4d4)))    // VOU SP Color Data Read Channel Base Address of SP2
#define REG_MCU_VCR18       (*((volatile DWORD *) (REG_MCU_BASE+0x4e0)))    // VOU Teletext Read Channel Base Address
#define REG_MCU_VCR19       (*((volatile DWORD *) (REG_MCU_BASE+0x4e4)))    // VOU Teletext Read Channel Read Address
#define REG_MCU_VCR1A       (*((volatile DWORD *) (REG_MCU_BASE+0x4e8)))    // VOU Teletext Read Address Upper Boundary
#define REG_MCU_VCR1B       (*((volatile DWORD *) (REG_MCU_BASE+0x4ec)))    // VOU Teletext Read Address Lower Boundary
#define REG_MCU_VCR1C       (*((volatile DWORD *) (REG_MCU_BASE+0x4f0)))    // VOU Teletext Read Channel FIFO Status Register
#define REG_MCU_VCR20       (*((volatile DWORD *) (REG_MCU_BASE+0x500)))    // VOU OSD Read Channel Base Address
#define REG_MCU_VCR21       (*((volatile DWORD *) (REG_MCU_BASE+0x504)))    // VOU OSD Read Channel Base Address
#define REG_MCU_VCR22       (*((volatile DWORD *) (REG_MCU_BASE+0x508)))    // VOU OSD Read Channel Width/Height
#define REG_MCU_VCR23       (*((volatile DWORD *) (REG_MCU_BASE+0x50c)))    // VOU OSD Read Channel X, Y Direction Increment
#define REG_MCU_VCR24       (*((volatile DWORD *) (REG_MCU_BASE+0x510)))    // VOU OSD Read Channel FIFO Status Register
#define REG_MCU_VCR25       (*((volatile DWORD *) (REG_MCU_BASE+0x51c)))    // VOU OSD upscalling register

#define REG_MCU_SCR10       (*((volatile DWORD *) (REG_MCU_BASE+0x5c0)))    // SERVO EDC Read Channel Base Address
#define REG_MCU_SCR11       (*((volatile DWORD *) (REG_MCU_BASE+0x5c4)))    // SERVO EDC Read Channel Read Address
#define REG_MCU_SCR12       (*((volatile DWORD *) (REG_MCU_BASE+0x5c8)))    // SERVO EDC Read Channel X, Y Direction Increment
#define REG_MCU_SCR13       (*((volatile DWORD *) (REG_MCU_BASE+0x5cc)))    // SERVO EDC Read Channel X, Y Direction Sub-Increment
#define REG_MCU_SCR14       (*((volatile DWORD *) (REG_MCU_BASE+0x5d0)))    // SERVO EDC Read Channel FIFO Status Register
#define REG_MCU_SCR15       (*((volatile DWORD *) (REG_MCU_BASE+0x5d4)))    // SERVO EDC Read Channel Width/Height
#define REG_MCU_SCR16       (*((volatile DWORD *) (REG_MCU_BASE+0x5d8)))    // SERVO EDC Read Channel Sub-Block Width/Height
#define REG_MCU_SCR18       (*((volatile DWORD *) (REG_MCU_BASE+0x5e0)))    // SERVO ECC Read Channel Base Address
#define REG_MCU_SCR19       (*((volatile DWORD *) (REG_MCU_BASE+0x5e4)))    // SERVO ECC Read Channel Base Address
#define REG_MCU_SCR1A       (*((volatile DWORD *) (REG_MCU_BASE+0x5e8)))    // SERVO ECC Read Channel X, Y Direction Increment
#define REG_MCU_SCR1B       (*((volatile DWORD *) (REG_MCU_BASE+0x5ec)))    // SERVO ECC Read Channel X, Y Direction Sub-Increment
#define REG_MCU_SCR1C       (*((volatile DWORD *) (REG_MCU_BASE+0x5f0)))    // SERVO ECC Read Channel FIFO Status Register
#define REG_MCU_SCR1D       (*((volatile DWORD *) (REG_MCU_BASE+0x5f4)))    // SERVO ECC Channel Setting / Q-Parity Offset
#define REG_MCU_SCR1E       (*((volatile DWORD *) (REG_MCU_BASE+0x5f8)))    // SERVO ECC Read Channel Width/Height
#define REG_MCU_SCR1F       (*((volatile DWORD *) (REG_MCU_BASE+0x5fc)))    // SERVO ECC Read Channel Sub-Block Width/Height


// Write Protection Registers
// Area 0~3 won't let data write to dram but area 4~5 will.
#define REG_MCU_WPROTEN     (*((volatile DWORD *) (REG_MCU_BASE+0x580)))    // write protection enable register
#define REG_MCU_WP0BASE     (*((volatile DWORD *) (REG_MCU_BASE+0x584)))    // write protection area 0 address base address, 64-bit alignment
#define REG_MCU_WP0SIZE     (*((volatile DWORD *) (REG_MCU_BASE+0x588)))    // write protection area 0 address upper boundary, 64-bit alignment
#define REG_MCU_WP1BASE     (*((volatile DWORD *) (REG_MCU_BASE+0x58c)))    // write protection area 1 address base address, 64-bit alignment
#define REG_MCU_WP1SIZE     (*((volatile DWORD *) (REG_MCU_BASE+0x590)))    // write protection area 1 address upper boundary, 64-bit alignment
#define REG_MCU_WP2BASE     (*((volatile DWORD *) (REG_MCU_BASE+0x594)))    // write protection area 2 address base address, 64-bit alignment
#define REG_MCU_WP2SIZE     (*((volatile DWORD *) (REG_MCU_BASE+0x598)))    // write protection area 2 address upper boundary, 64-bit alignment
#define REG_MCU_WP3BASE     (*((volatile DWORD *) (REG_MCU_BASE+0x59c)))    // write protection area 3 address base address, 64-bit alignment
#define REG_MCU_WP3SIZE     (*((volatile DWORD *) (REG_MCU_BASE+0x5a0)))    // write protection area 3 address upper boundary, 64-bit alignment
#define REG_MCU_WP4BASE     (*((volatile DWORD *) (REG_MCU_BASE+0x5a4)))    // write protection area 4 address base address, 64-bit alignment
#define REG_MCU_WP4SIZE     (*((volatile DWORD *) (REG_MCU_BASE+0x5a8)))    // write protection area 4 address upper boundary, 64-bit alignment
#define REG_MCU_WP5BASE     (*((volatile DWORD *) (REG_MCU_BASE+0x5ac)))    // write protection area 5 address base address, 64-bit alignment
#define REG_MCU_WP5SIZE     (*((volatile DWORD *) (REG_MCU_BASE+0x5b0)))    // write protection area 5 address upper boundary, 64-bit alignment
#define REG_MCU_WPSTATUS    (*((volatile DWORD *) (REG_MCU_BASE+0x5b4)))    // write protection status register

#define PREG_MCU_WP0BASE    ((volatile DWORD *) (REG_MCU_BASE+0x584))
#define PREG_MCU_WP0SIZE    ((volatile DWORD *) (REG_MCU_BASE+0x588))


#define REG_MCU_REMEN       (*((volatile DWORD *) (REG_MCU_BASE+0x680)))    // Buffer Remainder Enable Register