📄 hio.c
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VOID _IIC_SetACK (PI2C_CONFIG pConfig){ _I2C_Set_SDAT_LOW (pConfig); _I2C_Set_SCLK_HIGH (pConfig); _I2C_Set_SCLK_LOW (pConfig);}VOID _IIC_STOP (PI2C_CONFIG pConfig){ _I2C_Set_SDAT_LOW(pConfig); _I2C_Set_SCLK_HIGH(pConfig); _I2C_Set_SDAT_HIGH(pConfig);}VOID _I2C_Set_SDAT_HIGH(PI2C_CONFIG pConfig){ _Delay_I2C();//Alan075 HAL_WriteGPC( PIN_SDAT, 1);
HAL_WriteGPIO(pConfig->bIOGroup, pConfig->bSDAT_Pin, 1);
}VOID _I2C_Set_SCLK_HIGH(PI2C_CONFIG pConfig){ _Delay_I2C();//Alan075 HAL_WriteGPC( PIN_SCLK, 1);
HAL_WriteGPIO(pConfig->bIOGroup, pConfig->bSCLK_Pin, 1);
}VOID _I2C_Set_SDAT_LOW(PI2C_CONFIG pConfig){ _Delay_I2C();//Alan075 HAL_WriteGPC( PIN_SDAT, 0); HAL_WriteGPIO(pConfig->bIOGroup, pConfig->bSDAT_Pin, 0);
}VOID _I2C_Set_SCLK_LOW(PI2C_CONFIG pConfig){ _Delay_I2C();//Alan075 HAL_WriteGPC( PIN_SCLK, 0);
HAL_WriteGPIO(pConfig->bIOGroup, pConfig->bSCLK_Pin, 0);
}BYTE _I2C_Get_SDAT(PI2C_CONFIG pConfig){ _Delay_I2C();//Alan075 return ( HAL_ReadGPC( PIN_SDAT) );
return (HAL_ReadGPIO(pConfig->bIOGroup, pConfig->bSDAT_Pin));
}#endif //#ifdef SUPPORT_I2C
//**********************************************************************
// Description : DRAM Copy from one DRAM location to another DRAM location
// Arguments : dwSrc: the source DRAM location
// : dwDst: The destination DRAM location
// : dwLen: copy length in BYTE
// Return : None
//*********************************************************************
void HAL_CopyDRAM(DWORD dwSrc, DWORD dwDst, DWORD dwLen) //test OK
{
DWORD dwIndx;
//disable/flush cache
//REG_PLAT_CACHE_CONTROL |= CACHE_FLUSH_DCACHE; //dump-in OK => do flush immediately?
PLAT_PROC1_DCACHE_FLUSH;
//JPU Bitmap copy is faster=> consider later ?
if ( (dwSrc%4) || (dwDst%4) )
{
//Copy BYTE by BYTE
for ( dwIndx=0; dwIndx<dwLen; dwIndx++, dwSrc++, dwDst++)
{
*((volatile BYTE *)dwDst ) = *((volatile BYTE *)dwSrc );
}
}
else
{
//Copy DWORD by DWORD
for ( dwIndx=0; dwIndx<dwLen/4; dwIndx++, dwSrc+=4, dwDst+=4)
{
*((volatile DWORD *)dwDst ) = *((volatile DWORD *)dwSrc );
}
for ( dwIndx=0; dwIndx<dwLen%4; dwIndx++, dwSrc++, dwDst++)
{
*((volatile BYTE *)dwDst ) = *((volatile BYTE *)dwSrc );
}
}
}
//dwLen: byte length; dwOffset: byte offset relative to the beginning of User Data
void HAL_DumpUserData( BYTE* pbBuf, DWORD dwLen, DWORD dwPosition ) //test OK
{
DWORD dwIndx;
//disable/flush cache
//REG_PLAT_CACHE_CONTROL |= CACHE_FLUSH_DCACHE; //dump-in OK => do flush immediately?
PLAT_PROC1_DCACHE_FLUSH;
//Copy BYTE by BYTE first
//JPU Bitmap copy is faster=> consider later ?
for ( dwIndx=0; dwIndx<dwLen; dwIndx++)
{
*(pbBuf+dwIndx) = *((volatile BYTE *) (dwPosition+dwIndx) );
}
}
// SYuan2.77-909P: Suuport to set UART TX , UART RX indendently
//****************************************************************************
//Description : Set UART baud rate value
// Argument : dwSysCLK, current system clock
// dwBaudRate, desired baudrate value
// dwPort, desired UART port
// return : none.
//***************************************************************
VOID HAL_UART_BaudRateSet(DWORD dwSysCLK, DWORD dwBaudRate, DWORD dwPort)
{ BYTE bPort;
//get UART port , ex: UART1 or UART2
bPort = GET_UART_PORT(dwPort);
bPort--;
//REG_PLAT_UART1_SCALER = (((SYSTEM_CLK*10)/(UART_BAUDRATE_QUAD_SPEED*8))-5)/10; REG_PLAT_UART_SCALER(bPort) = (((dwSysCLK*10)/(dwBaudRate*8))-5)/10;}// SYuan2.77-909P: Suuport to set UART TX , UART RX indendently
//**************************************************************
//function :HAL_UART_Disable
//descriptor : Disable all possible UART path.
//arguments : dwPort :spcify UART port. ex: UART1_TX or UART1_RX .
//return :none
//***************************************************************
VOID HAL_UART_Disable(DWORD dwPort)
{ BYTE bPort;
//get UART port , ex: UART1 or UART2
bPort = GET_UART_PORT(dwPort);
bPort--;
// LLY2.60, porting the necessary code for CT909P IC
// UART are shared the same pin w/ other function,
// So, if disable UART function, must release it to others.
#ifdef CT909P_IC_SYSTEM
if(dwPort == HAL_UART1_TX)
{
//Disable all possible UART1 TX path
//[1] from SPI -- GPA[[1], so clear GPAMux[4]=0
REG_PLAT_GPA_MUX &= ~(1L<<4);
//[2] from card reader -- GPC[7], so clear GPCMux[12]=0
REG_PLAT_GPC_MUX &= ~(1L<<12);
//[3] from NIM -- GPG[1], so clear GPG[6]=0
REG_PLAT_GPG_MUX &= ~(1L<<6);
//REG_PLAT_UART_CONTROL(bPort) = 0;
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_TX_ENABLE);
}
else if(dwPort == HAL_UART1_RX)
{
//Disable all possible UART1 RX path
//[1] from SPI -- GPA[0], so clear GPAMux[1]=0
REG_PLAT_GPA_MUX &= ~(1L<<1);
//[2] from card reader -- GPC[8], so clear GPCMux[16]=0
REG_PLAT_GPC_MUX &= ~(1L<<16);
//[3] from NIM -- GPG[0], so clear GPGMux[2]=0
REG_PLAT_GPG_MUX &= ~(1L<<2);
//REG_PLAT_UART_CONTROL(bPort) = 0;
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_RX_ENABLE);
}
else if(dwPort == HAL_UART2_TX)
{
//Disable all possible UART2 TX path
//[1] from SPI -- GPA[3], so clear GPAMux[11]=0
REG_PLAT_GPA_MUX &= ~(1L<<11);
//[2] from NIM -- GPG[3], so clear GPGMux[15]=0
REG_PLAT_GPG_MUX &= ~(1L<<15);
//[3] from expand GPIO -- GPC[4], so clear GPCMux[5]=0
REG_PLAT_GPC_MUX &= ~(1L<<5);
//REG_PLAT_UART_CONTROL(bPort) = 0;
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_TX_ENABLE);
}
else if(dwPort == HAL_UART2_RX)
{
//Disable all poosible UART RX path
//[1] from SPI -- GPA[2], so clear GPAMux[8]=0
REG_PLAT_GPA_MUX &= ~(1L<<8);
//[2] from NIM -- GPG[2], so clear GPGMux[11]=0
REG_PLAT_GPG_MUX &= ~(1L<<11);
//[3] from expand GPIO -- GPC[5], so clear GPCMux[7]=0
REG_PLAT_GPC_MUX &= ~(1L<<7);
//REG_PLAT_UART_CONTROL(bPort) = 0;
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_RX_ENABLE);
}
#endif // #ifdef CT909P_IC_SYSTEM
// LLY2.75, disable UART pin control for CT909G
#ifdef CT909G_IC_SYSTEM
#if 0
if(dwPort == HAL_UART1)
{
// set bit[12:8] of System Pin-Use Register 0 to disable UART1
REG_PLAT_SYS_PIN_USE0 &= ~(0x1fL<<8);
REG_PLAT_UART_CONTROL(bPort) &= ~(UART_RX_ENABLE|UART_TX_ENABLE);
}
else
#endif
if(dwPort == HAL_UART1_TX)
{
// set bit[12:10] of System Pin-Use Register 0 to disable UART1
REG_PLAT_SYS_PIN_USE0 &= ~(0x1CL<<8);
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_TX_ENABLE);
}
else if (dwPort == HAL_UART1_RX)
{
// set bit[9:8] of System Pin-Use Register 0 to disable UART1
REG_PLAT_SYS_PIN_USE0 &= ~(0x3L<<8);
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_RX_ENABLE);
}
#if 0
else if(dwPort == HAL_UART2)
{
// set bit[1:0] of System Pin-Use Register 0 to disable UART2
REG_PLAT_SYS_PIN_USE0 &= ~(0x3L);
REG_PLAT_UART_CONTROL(bPort) &= ~(UART_RX_ENABLE|UART_TX_ENABLE);
}
#endif
else if(dwPort == HAL_UART2_TX)
{
// set bit[1] of System Pin-Use Register 0 to disable UART2
REG_PLAT_SYS_PIN_USE0 &= ~(0x2L);
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_TX_ENABLE);
}
else if (dwPort == HAL_UART2_RX)
{
// set bit[0] of System Pin-Use Register 0 to disable UART2
REG_PLAT_SYS_PIN_USE0 &= ~(0x1L);
REG_PLAT_UART_CONTROL(bPort) &= ~(0xfffffffC+UART_RX_ENABLE);
}
#endif // #ifdef CT909G_IC_SYSTEM
//REG_PLAT_UART_CONTROL(bPort) &= ~(UART_RX_ENABLE|UART_TX_ENABLE);
//REG_PLAT_UART_CONTROL(bPort) = 0;
}//SYuan2.77-909P: support to set UART2 TX & RX independently.
//**************************************************************************
//function : HAL_UART_Enable
//description : Enable UART TX, RX path.
//arguments : dwport : specify UART port. ex UART1_TX or UART1_RX or UART2_TX or UART_RX
// bPath : specify UART GPIO path. ex: NIM_PATH ...etc.
//return :none.
//****************************************************************************
VOID HAL_UART_Enable(DWORD dwPort, BYTE bPath)
{ BYTE bPort;
DWORD dwBug;
//get UART port , ex: UART1 or UART2
bPort = GET_UART_PORT(dwPort);
bPort--;
#ifdef CT909G_IC_SYSTEM
#if 0
if(dwPort == HAL_UART1)
{
// LLY2.56, default configuration for CT909G EV board
// UART1_TX: using GPA[10], so set system pin-use0[12]=1
// UART1_RX: using GPA[6], so set system pin-use0[8]=1, [24, 16, 0]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<12) + (0x1L<<8);
REG_PLAT_SYS_PIN_USE0 &= ~((0x1L<<24)+(0x1L<<16)+(0x1L));
REG_PLAT_UART_CONTROL(bPort) = (UART_RX_ENABLE|UART_TX_ENABLE);
}
else
#endif
if(dwPort == HAL_UART1_TX)
{
//for Debug Mode, __dwDebugMode must be set first. [8~11] be used indicate UART1_TX.
//bPath = (__dwDebugMode & 0xf00) >> 8;
if (bPath == VFD_CS_PATH) //GPA_10
{
// default configuration for CT909G EV board
// UART1_TX: using GPA[10], so set system pin-use0[12]=1
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<12);
REG_PLAT_UART_CONTROL(bPort) |= (UART_TX_ENABLE);
}
else if (bPath == VFD_PATH) //GPA_9
{
// default configuration for CT909G EV board
// UART1_TX: using GPA[9], so set system pin-use0[11]=1 , [27]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<11);
REG_PLAT_SYS_PIN_USE0 &= ~(0x1L<<27);
REG_PLAT_UART_CONTROL(bPort) |= (UART_TX_ENABLE);
}
else if (bPath == IO_MUTE_PATH) //GPA_4
{
// default configuration for CT909G EV board
// UART1_TX: using GPA[4], so set system pin-use0[10]=1 , [26]=0, [17]=0, [10]=0, [1]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<10);
REG_PLAT_SYS_PIN_USE0 &= ~((0x1L<<26)+(0x1L<<17)+(0x1L<<1));
REG_PLAT_UART_CONTROL(bPort) |= (UART_TX_ENABLE);
}
}
else if(dwPort == HAL_UART1_RX)
{
//for Debug Mode, __dwDebugMode must be set first. [12 ~ 15] be used indicate UART1_RX.
//bPath = (__dwDebugMode & 0xf000) >> 12;
if (bPath == SCART_PATH) //GPA_6
{
// default configuration for CT909G EV board
// UART1_RX: using GPA[6], so set system pin-use0[8]=1, [24, 16, 0]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<8);
REG_PLAT_SYS_PIN_USE0 &= ~((0x1L<<24)+(0x1L<<16)+(0x1L));
REG_PLAT_UART_CONTROL(bPort) |= (UART_RX_ENABLE);
}
else if (bPath == VFD_PATH) //GPA_11
{
// default configuration for CT909G EV board
// UART1_RX: using GPA[11], so set system pin-use0[9]=1, [25]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<9);
REG_PLAT_SYS_PIN_USE0 &= ~(0x1L<<25);
REG_PLAT_UART_CONTROL(bPort) |= (UART_RX_ENABLE);
}
}
else if(dwPort == HAL_UART2_TX)
{
//for Debug Mode, __dwDebugMode must be set first. [16 ~ 19] be used indicate UART2_TX.
//bPath = (__dwDebugMode & 0xf0000) >> 16;
if(bPath == IO_MUTE_PATH)
{
// default configuration for CT909G EV board
// UART1_RX: using GPA[4], so set system pin-use0[1]=1, [10, 17, 26]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<1);
REG_PLAT_SYS_PIN_USE0 &= ~((0x1L<<26)+(0x1L<<17)+(0x1L<<10));
REG_PLAT_UART_CONTROL(bPort) |= (UART_TX_ENABLE);
}
}
else if(dwPort == HAL_UART2_RX)
{
//for Debug Mode, __dwDebugMode must be set first. [20 ~ 23] be used indicate UART2_RX.
//bPath = (__dwDebugMode & 0xf00000) >> 20;
if(bPath == SCART_PATH)
{
// default configuration for CT909G EV board
// UART1_RX: using GPA[4], so set system pin-use0[0]=1, [8, 16, 24]=0
REG_PLAT_SYS_PIN_USE0 |= (0x1L<<1);
REG_PLAT_SYS_PIN_USE0 &= ~((0x1L<<24)+(0x1L<<16)+(0x1L<<8));
REG_PLAT_UART_CONTROL(bPort) |= (UART_RX_ENABLE);
}
}
#endif // #ifdef CT909G_IC_SYSTEM
// LLY2.11, disable DSU1 if enable UART1 only for DSU1/ UART1 shared case (128pin, ex 909R)#ifdef DSU1_UART1_SAME_PORT
dwPort &= (0x0000ff00); //don't care about TX, RX port.
if(dwPort == HAL_UART1)
{ //for Debug Mode, __dwDebugMode must be set first. [20 ~ 23] be used indicate UART2_RX.
//bPath = (__dwDebugMode & 0x00ff00) >> 8;
if(bPath != NOT_USED)
{
// disable bit[27]: DSU1 pin enable
REG_PLAT_MPLL_CONTROL &= ~(1<<27);
// enable bit[25]: UART1 use GPA[3:2]
REG_PLAT_MPLL_CONTROL |= (1<<25);
}
} REG_PLAT_UART_CONTROL(bPort) = (UART_RX_ENABLE|UART_TX_ENABLE);
#endif // #ifdef DSU1_UART1_SAME_PORT
// LLY2.50, add for CT909P to config UART multi-function selection
#ifdef CT909P_IC_SYSTEM
if(dwPort == HAL_UART1_TX)
{
//for Debug Mode, __dwDebugMode must be set first. [8~11] be used indicate UART1_TX.
//bPath = (__dwDebugMode & 0xf00) >> 8;
if (bPath == NIM_PATH)
{
//USE GPG[1] for TX
//Must clear GPGMux[7] as 0, and set GPGMux[6]=1 for UART1 TX
REG_PLAT_GPG_MUX &= ~(0xf0L);
REG_PLAT_GPG_MUX |= (1L<<6);
//need disable other UART1 TX Path
// [1] from SPI, so clear GPAMux[4]=0
REG_PLAT_GPA_MUX &= ~(1L<<4);
// [2] from card reader, so clear GPCMux[12]
REG_PLAT_GPC_MUX &= ~(1L<<12);
// LLY2.75, if enable define "USE_GPA21_CTL_74244" then do following control.
// Now, only CT909P_P3 and CT956A system board support it.
#ifdef USE_GPA21_CTL_74244
// LLY2.51, porting Chuan's code to enable GPA[21] as GPO and output 1
// For simple method: just set GPAMux[22]=1 to reach this goal
// Notice: must check if it's ok by the correct method.
//REG_PLAT_GPA_MUX |= (1L << 22);
HAL_WriteGPIO(GPIO_A, 21, 1);
#endif // #ifdef USE_GPA21_CTL_74244
REG_PLAT_UART_CONTROL(bPort) |= (UART_TX_ENABLE);
}
else if (bPath == SPI_PATH)
{
//USE GPA[1] for TX
//must clear GPAMux[5] as o and set GPAMux[4] =1 for UART1 TX
REG_PLAT_GPA_MUX &= ~(0x38L);
REG_PLAT_GPA_MUX |= (1L<<4);
//need disable other UART1 TX path
// [1] from card reader, so clear GPCMux[12]
REG_PLAT_GPC_MUX &= ~(1L<<12);
// [2] from NIM, so clear GPG[6]=0
REG_PLAT_GPG_MUX &= ~(1L<<6);
// LLY2.75, if enable define "USE_GPA21_CTL_74244" then do following control.
// Now, only CT909P_P3 and CT956A system board support it.
#ifdef USE_GPA21_CTL_74244
// LLY2.51, porting Chuan's code to enable GPA[21] as GPO and output 1
// For simple method: just set GPAMux[22]=1 to reach this goal
// Notice: must check if it's ok by the correct metho⌨️ 快捷键说明
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