hio.c

ct952 source code use for Digital Frame Photo

        }
        else if(dwPort==3)
        {
            // GPAMux[9]=1, GPAMux[11:10]=0
            REG_PLAT_GPA_MUX &= ~(0x7L<<9);
            REG_PLAT_GPA_MUX |= (0x1L<<9);
        }
        else if(dwPort==4 || dwPort==5 || dwPort==12 || dwPort==13 || dwPort==24 || dwPort==25)
        {
            // GPAMux[12]=1; GPAMux[13, 16, 24]=0
            REG_PLAT_GPA_MUX &= ~((0x1L<<13) + (0x1L<<16) + (0x1L<<24));
            REG_PLAT_GPA_MUX |= (0x1L<<12);
        }
        else if(dwPort>=6 && dwPort<=11)
        {
            // GPAMux[14]=1; GPAMux[15]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<15);
            REG_PLAT_GPA_MUX |= (0x1L<<14);
        }
        else if(dwPort>=14 && dwPort<=19)
        {
            // GPAMux[17]=1; GPAMux[18]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<18);
            REG_PLAT_GPA_MUX |= (0x1L<<17);
        }
        else if(dwPort==20)
        {
            // GPAMux[20]=1; GPAMux[19]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<19);
            REG_PLAT_GPA_MUX |= (0x1L<<20);
        }
        else if(dwPort==21)
        {
            // GPAMux[22]=1; GPAMux[21]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<21);
            REG_PLAT_GPA_MUX |= (0x1L<<22);
        }
        else if(dwPort==22 || dwPort==23)
        {
            // GPAMux[23]=1
            REG_PLAT_GPA_MUX |= (0x1L<<23);
        }
        else if(dwPort>=26 && dwPort<=31)
        {
            // GPAMux[25]=1, GPAMux[26]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<26);
            REG_PLAT_GPA_MUX |= (0x1L<<25);
        }

#endif  // #ifdef CT909P_IC_SYSTEM

        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPA_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_B)
    {
        // LLY2.56, GPB control can be handled by MPEG part @ CT909G
        // And, must set bit[16]:GPB_EN, must set as 1, then can control GPB by MPEG part
        // Notice: default disable MPEG path otherwise can't access servo internal H/W block
#if 0//def  CT909G_IC_SYSTEM
        REG_PLAT_GPB_IO_DIR_CONTROL |= dwDesiredPort + (0x1L<<16);
#else   // #ifdef CT909G_IC_SYTEM
        // LLY2.51, do index map for GPB since it's different @ CT909P for function selection and IO Direction port
#ifdef  CT909P_IC_SYSTEM
        BYTE    aMap[6]={8, 6, 15, 16, 17, 18};

        // LLT2.77, remove the error protection before disable interrupt action.
        // Otherwise, nobody release the interrupt.
#if 0
        if(dwPort >= 6)
        {
            DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: Not supported GPB port\n");
            return FALSE;
        }
#endif  // #if 0

        // LLY2.53, fix coding error (forget to do shift operation).
        dwDesiredPort = (1<<aMap[dwPort]);
#endif  // #ifdef CT909P_IC_SYSTEM

        // Set GPB output function selection register as GPIO mode by 0
        // LLY2.15, only can modify the desired pin
        REG_SERVO_GPB_FUNC_SEL &= ~(dwDesiredPort);

        // Set 1 to enable the desired port as input mode
        REG_SERVO_GPB_IO_DIR_CONTROL |= dwDesiredPort;
#endif  // #ifdef CT909G_IC_SYSTEM

    }
#ifdef  CT909P_IC_SYSTEM
    else if(bGroup==GPIO_C)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPC_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_D)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPD_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_E)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPE_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_F)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPF_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_G)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPG_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_H)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPH_IO_DIR_CONTROL |= dwDesiredPort;
    }
#endif  // #ifdef CT909P_IC_SYSTEM
    // GPCDE same register of CT909R
#ifdef CT909R_IC_SYSTEM
    else if( (bGroup>=GPIO_C) && (bGroup<=GPIO_E) )
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPCDE_IO_DIR_CONTROL |= dwDesiredPort;
    }
    else if(bGroup==GPIO_F)
    {
    }
#endif  // #ifdef CT909R_IC_SYSTEM

    // LLY2.56, support GPC @ CT909G
#ifdef  CT909G_IC_SYSTEM
    else if(bGroup == GPIO_C)
    {
        // Set 1 to enable the desired port as input mode
        REG_PLAT_GPC_IO_DIR_CONTROL |= dwDesiredPort;
    }
#endif  // #ifdef CT909G_IC_SYSTEM

    // Release the interrupt
    OS_RESTORE_INTERRUPTS(dwSaveInt);

    // Read-back the desired port value

    if(bGroup==GPIO_A)
    {
        if( REG_PLAT_GPA_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
    else if(bGroup==GPIO_B)
    {
        // LLY2.56, GPB control can be handled by MPEG part @ CT909G
        // Notice: default disable MPEG path otherwise can't access servo internal H/W block
#if 0//def  CT909G_IC_SYSTEM
        if( REG_PLAT_GPB_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
#else   // #ifdef CT909G_IC_SYTEM
        // LLY2.51, it's un-necessary to index map for GPB INDATA port
        // So, must re-calculate desired port again.
#ifdef  CT909P_IC_SYSTEM
        dwDesiredPort = (1<<dwPort);
#endif  // #ifdef CT909P_IC_SYSTEM

        if(REG_SERVO_GPB_INDATA & dwDesiredPort)
        {
            return 1;
        }
        else
        {
            return 0;
        }
#endif  // #ifdef CT909G_IC_SYSTEM

    }
#ifdef  CT909P_IC_SYSTEM
    else if(bGroup==GPIO_C)
    {
        if( REG_PLAT_GPC_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
    else if(bGroup==GPIO_D)
    {
        if( REG_PLAT_GPD_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
    else if(bGroup==GPIO_E)
    {
        if( REG_PLAT_GPE_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
    else if(bGroup==GPIO_F)
    {
        if( REG_PLAT_GPF_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
    else if(bGroup==GPIO_G)
    {
        if( REG_PLAT_GPG_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
    else if(bGroup==GPIO_H)
    {
        if( REG_PLAT_GPH_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
#endif  // #ifdef CT909P_IC_SYSTEM
    // GPCDE @ same register of CT909R
#ifdef CT909R_IC_SYSTEM
    else if( (bGroup >= GPIO_C) && (bGroup <= GPIO_E) )
    {
        if(REG_PLAT_GPCDE_CLEAR & dwDesiredPort)
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
#endif  // #ifdef CT909R_IC_SYSTEM
    // LLY2.56, add GPC part for CT909G
#ifdef  CT909G_IC_SYSTEM
    else if(bGroup==GPIO_C)
    {
        if( REG_PLAT_GPC_CLEAR & dwDesiredPort )
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
#endif  // #ifdef CT909G_IC_SYSTEM

#ifdef  ENABLE_EXPAND_GPIO
    else if(bGroup==GPIO_EXP)
    {
        if(REG_PLAT_PANEL_KD & dwDesiredPort)
        {
            return 1;
        }
        else
        {
            return 0;
        }
    }
#endif  // #ifdef  ENABLE_EXPAND_GPIO

    return 0;
 }


//  ************************************************************************************************
//  Function    :   HAL_WriteGPIO
//  Description :   PH or PL the desired GPA port
//  Arguments   :   bGroup: specify the GPIO group
//                  dwPort: port #
//                  bValue: 1: High 0: Low
//  Notice      :   if set direct value as 0, it means output mode
//                  if set direct value as 1, it means input mode
//                  Must disable interrupt first since GPIO maybe accessed by different thread
//  ***********************************************************************************************
// LLY2.13, add for expend GPIO
// LLY2.15, modify the procedure for GPIO CDEF group
// LLY2.50, modify the procedure to support extra CT909P GPIO group
void    HAL_WriteGPIO(BYTE bGroup, DWORD dwPort, BYTE bValue)
{
    DWORD   dwSaveInt;

    // Used to keep desired port position, one port -> one position
    DWORD   dwDesiredPort;

#ifdef CT909R_IC_SYSTEM
    if(bGroup == GPIO_F)
    {
        DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: Not implement GPIO group\n");
        return;
    }
#endif  // #ifdef CT909R_IC_SYSTEM

    if(bGroup==GPIO_EXP)
    {
        // LLY2.16, go S/W Expand GPIO path
#ifdef  SW_EXPAND_GPIO
        _SW_Expand_GPO(dwPort, bValue);
        return;
#else   // #ifdef SW_EXPAND_GPIO
        // LLY2.15, must swap for desired port bit[7:0], bit[15:8]
        // ie. port 0 --> port7; port 8 --> port15
        // Since, IC design will output bit[0] first for Expand GPIO GPO mode
        dwPort = (dwPort&0x8) | ((~dwPort)&0x7);
        //DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Port: %lx\n", dwPort);
#endif  // #ifdef SW_EXPAND_GPIO
    }

    // LLY2.50, do index map for GPB since it's different @ CT909P
#ifdef  CT909P_IC_SYSTEM
    if(bGroup==GPIO_B)
    {
        BYTE    aMap[6]={8, 6, 15, 16, 17, 18};

        if(dwPort >= 6)
        {
            DBG_Printf(DBG_THREAD_CHEERDVD, DBG_INFO_PRINTF, "Err: Not supported GPB port\n");
            return;
        }
        dwPort = aMap[dwPort];
    }
#endif  // #ifdef CT909P_IC_SYSTEM

    // Shift the desired port to final position first
    dwDesiredPort = (1<<dwPort);

#ifdef CT909R_IC_SYSTEM
    // Shift left again for GPIO CDE, since they shared the same register @ CT909R
    if(bGroup==GPIO_D)
    {
        // Shift left 8 bit since GPIO D @ bit[15:8] first
        dwDesiredPort = (dwDesiredPort << 8);
    }
    else if(bGroup==GPIO_E)
    {
        // Shift left 16 bit since GPIO E @ bit [24:16] first
        dwDesiredPort = (dwDesiredPort << 16);
    }
#endif  // #ifdef CT909R_IC_SYSTEM

    OS_DISABLE_INTERRUPTS(dwSaveInt);
    if(bGroup==GPIO_A)
    {
        // LLY2.51, config GPA Mux selection register for using GPA as GPIO @ CT909P
#ifdef  CT909P_IC_SYSTEM
        if(dwPort==0)
        {
            // GPAMux[0]=1, GPAMux[2:1]=0
            REG_PLAT_GPA_MUX &= ~(0x7L);
            REG_PLAT_GPA_MUX |= 0x1L;
        }
        else if(dwPort==1)
        {
            // GPAMux[3]=1, GPAMux[5:4]=0
            REG_PLAT_GPA_MUX &= ~(0x7L<<3);
            REG_PLAT_GPA_MUX |= (0x1L<<3);
        }
        else if(dwPort==2)
        {
            // GPAMux[6]=1, GPAMux[8:7]=0
            REG_PLAT_GPA_MUX &= ~(0x7L<<6);
            REG_PLAT_GPA_MUX |= (0x1L<<6);
        }
        else if(dwPort==3)
        {
            // GPAMux[9]=1, GPAMux[11:10]=0
            REG_PLAT_GPA_MUX &= ~(0x7L<<9);
            REG_PLAT_GPA_MUX |= (0x1L<<9);
        }
        else if(dwPort==4 || dwPort==5 || dwPort==12 || dwPort==13 || dwPort==24 || dwPort==25)
        {
            // GPAMux[12]=1; GPAMux[13, 16, 24]=0
            REG_PLAT_GPA_MUX &= ~((0x1L<<13) + (0x1L<<16) + (0x1L<<24));
            REG_PLAT_GPA_MUX |= (0x1L<<12);
        }
        else if(dwPort>=6 && dwPort<=11)
        {
            // GPAMux[14]=1; GPAMux[15]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<15);
            REG_PLAT_GPA_MUX |= (0x1L<<14);
        }
        else if(dwPort>=14 && dwPort<=19)
        {
            // GPAMux[17]=1; GPAMux[18]=0
            REG_PLAT_GPA_MUX &= ~(0x1L<<18);
            REG_PLAT_GPA_MUX |= (0x1L<<17);
        }