📄 ctkav_vdec.h
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#define REG_SIDEINFO_PIC_WRADR (*(volatile DWORD *)(REG_SIDEINFO_BASE+0xCL)) // 0x224C#define REG_SIDEINFO_ROW_DEFADR (*(volatile DWORD *)(REG_SIDEINFO_BASE+0x10L)) // 0x2250#define REG_SIDEINFO_RDMBCNT (*(volatile DWORD *)(REG_SIDEINFO_BASE+0x14L)) // 0x2254#define REG_SIDEINFO_WRMBCNT (*(volatile DWORD *)(REG_SIDEINFO_BASE+0x18L)) // 0x2258#define REG_SIDEINFO_CTL (*(volatile DWORD *)(REG_SIDEINFO_BASE+0x1CL)) // 0x225C#define REG_SIDEINFO_VALUE (*(volatile DWORD *)(REG_SIDEINFO_BASE+0x20L)) // 0x2260#define REG_VDEC_CG_EN (*(volatile DWORD *)(REG_MC_BASE+0x360L)) // 0x2470#define REG_VDEC_CG_CLR (*(volatile DWORD *)(REG_MC_BASE+0x364L)) // 0x2474#if defined(CT909P_IC_SYSTEM) || defined(CT909G_IC_SYSTEM)#define REG_VDEC_BUG_SEL (*(volatile DWORD *)(REG_MC_BASE+0x368L)) // 0x2478#endif// MB_CTL0#define VLD_INTRA (0x1L) // MB_CTL0[0]#define VLD_MB_SKIP (0x2L) // MB_CTL0[1]#define VLD_USE_INTRA_DC_VLC (0x4L) // MB_CTL0[2]#define VLD_CBP5_0 (0x1F8L) // MB_CTL0[8:3]#define VLD_FIRST_MB (0x200L) // MB_CTL0[9]#define VLD_ACPRED_EN (0x400L) // MB_CTL0[10]#define VLD_QUANT_SCALE (0x3F800L) // MB_CTL0[17:11]#define VLD_NEW_UP (0x10000L) // MB_CTL0[16]#define VLD_NEW_PACK (0x20000L) // MB_CTL0[17]#define VLD_DCT_TYPE (0x40000L) // MB_CTL0[18]#define VLD_FIELD_PRED (0x80000L) // MB_CTL0[19]// MB_CTL1#define VLD_FORWARD (0x0004L) // MB_CTL1[2] #define VLD_BACKWARD (0x0008L) // MB_CTL1[3]#define VLD_FOURMV (0x0010L) // MB_CTL1[4]#define VLD_MCCASE0 (0x0020L) // MB_CTL1[5] #define VLD_MCCASE1 (0x0040L) // MB_CTL1[6] #define VLD_MCCASE2 (0x0080L) // MB_CTL1[7] #define VLD_MCCASE3 (0x0100L) // MB_CTL1[8] #define VLD_MCCASE4 (0x0200L) // MB_CTL1[9]#define VLD_MCCASE5 (0x0400L) // MB_CTL1[10] #define VLD_MCCASE6 (0x0800L) // MB_CTL1[11] #define VLD_MCCASE7 (0x1000L) // MB_CTL1[12] #define VLD_MCCASE8 (0x2000L) // MB_CTL1[13]#define VLD_GMC_EN (0x4000L) // MB_CTL1[14]#define VLD_DIRECT (0x8000L) // MB_CTL1[15]#define VLD_FOR_TOP (0x10000L) // MB_CTL1[16] #define VLD_FOR_BOT (0x20000L) // MB_CTL1[17]#define VLD_BACK_TOP (0x40000L) // MB_CTL1[18]#define VLD_BACK_BOT (0x80000L) // MB_CTL1[19]#define VLD_MCCASE (0x3FE0L) // MB_CTL1[13:5]// VLD_CTL#define VLD_DEC (0x1L) // VLD_CTL[0] #define VLD_EXE (0x2L) // VLD_CTL[1]#define VLD_MBAI (0x4L) // VLD_CTL[2]#define VLD_MBTYPE (0x8L) // VLD_CTL[3]#define VLD_CBP (0x10L) // VLD_CTL[4]#define VLD_MV_MP2 (0x20L) // VLD_CTL[5]#define VLD_MCBPC (0x40) // VLD_CTL[6]#define VLD_CBPY (0x80) // VLD_CTL[7]#define VLD_MODB (0x100) // VLD_CTL[8]#define VLD_BMBTYPE (0x200) // VLD_CTL[9]#define VLD_QUANT (0x400) // VLD_CTL[10]#define VLD_MV_MP4 (0x800) // VLD_CTL[11]#define VLD_CBPI_311 (0x1000) // VLD_CTL[12]#define VLD_CBPP_311 (0x2000) // VLD_CTL[13]#define VLD_MV_311 (0x4000) // VLD_CTL[14]#define VLD_NUM (15) // VLD_CTL[20:15]#define VLD_FNS (0x200000L) // VLD_CTL[21]#define VLD_RESET_MV (0x800000L) // VLD_CTL[23]#define VLD_UPDATE_MV (0x1000000L) // VLD_CTL[24]#define VLD_SWAP_MV (0x2000000L) // VLD_CTL[25]#define VLD_MV_GO (0x4000000L) // VLD_CTL[26]#define VLD_GMV_GO (0x8000000L) // VLD_CTL[27]#define VLD_FNS_SPECIFY (0x10000000L) // VLD_CTL[28]#define VLD_BP_MODE (0x20000000L) // VLD_CTL[29]#define VLD_LOCALRESET (0x80000000L) // VLD_CTL[31]#define VLD_INTRA_CBPCY (22)// VLD_INFO#define VLD_JPEG_MODE (0x1L) // VLD_INFO[0]#define VLD_MPEG1_MODE (0x2L) // VLD_INFO[1]#define VLD_MPEG2_MODE (0x4L) // VLD_INFO[2]#define VLD_MPEG4_MODE (0x8L) // VLD_INFO[3]#define VLD_DIVX311_MODE (0x10L) // VLD_INFO[4]#define VLD_PICTYPE (0x60L) // VLD_INFO[6:5]#define VLD_INTERLACED (0x80L) // VLD_INFO[7]#define VLD_DATA_PART (0x100L) // VLD_INFO[8]#define VLD_REVERSIBLE (0x200L) // VLD_INFO[9]#define VLD_SHORT_HEADER (0x400L) // VLD_INFO[10]#define VLD_INTRA_VLC_FORMAT (0x100000L) // VLD_INFO[20]#define VLD_BITS_REQ_EN (0x200000L) // VLD_INFO[21]#define VLD_NFL16 (0x400000L) // VLD_INFO[22]#define VLD_SINFO_EN (0x800000L) // VLD_INFO[23]// VLD_STATUS#define VLD_VAL (0x000FFFL) // VLD_STATUS[11:0]#define VLD_BAR_BITNUM (0x01F000L) // VLD_STATUS[16:12]#define VLD_N_BYTEALIGN (0x020000L) // VLD_STATUS[17]#define VLD_FSTART_CODE (0x040000L) // VLD_STATUS[18]#define VLD_FMV_DONE (0x1000000L) // VLD_STATUS[24]#define VLD_BMV_DONE (0x2000000L) // VLD_STATUS[25]#define VLD_MB_RDY (0x4000000L) // VLD_STATUS[26]#define VLD_LIMBIT16 (0x8000000L) // VLD_STATUS[27]#define VLD_SEL32 (0x020000L) // VLD_STATUS[17]#define VLD_MCBPC (0x40)#define VLD_CBPY (0x80)#define VLD_MODB (0x100)#define VLD_BMBTYPE (0x200)#define VLD_DBQUANT (0x400)#define VLD_MV_MP4 (0x800)#define VLD_CBPI_311 (0x1000)#define VLD_CBPP_311 (0x2000)#define VLD_MV_311 (0x4000)#define VLD_INTRA_CBPCY (22)// MBINT_CTL#define VLD_HDR_DONE (0x1L) // MBINT_CTL[0]#define VLD_RL_DONE (0x2L) // MBINT_CTL[1] #define VLD_PLA_ERR (0x4L) // MBINT_CTL[2] #define VLD_MC_DONE (0x8L) // MBINT_CTL[3] #define VLD_REGB_EN (0x400L) // MBINT_CTL[10] #define VLD_JPEG_ST (0x800L) // MBINT_CTL[11]// DEQ_CTL#define DEQ_VOP_START (0x1L)#define DEQ_ALTERNATE_SCAN (0x2L) // DEQ_CTL[1]#define DEQ_INTRA_DC_PRECISION (0xCL) // DEQ_CTL[3:2]#define DEQ_RESET_DC_PREC (0x10L) // DEQ_CTL[4]#define DEQ_RESET_QRAM_COUNTER (0x20L) // DEQ_CTL[5]// SIDEINFO_CTL#define SINFO_RDEN (0x1L)#define SINFO_WREN_PIC (0x2L)// SIDEINFO_VALUE#define SINFO_SIRD_READY (0x0400L)#define SINFO_SIWR_READY (0x0800L)#define SINFO_WR_DONE (0x1000L)// DRAM_xADR#define MC_FADR0 (REG_MC_DRAM_FADR0+0)#define MC_FADR1 (REG_MC_DRAM_FADR0+4)#define MC_FADR2 (REG_MC_DRAM_FADR0+8)#define MC_FADR3 (REG_MC_DRAM_FADR0+12)#define MC_FADR4 (REG_MC_DRAM_FADR0+16)#define MC_BADR0 (REG_MC_DRAM_FADR0+20)#define MC_BADR1 (REG_MC_DRAM_FADR0+24)#define MC_BADR2 (REG_MC_DRAM_FADR0+28)#define MC_BADR3 (REG_MC_DRAM_FADR0+32)#define MC_BADR4 (REG_MC_DRAM_FADR0+36)// MC_CTL#define MC_XY_CALC (0x10000)///////////////////////////////////////////////////////////////////////////////// SRAM Allocation Table: 2048 BYTE#define REG_SRAM_BASE (0xb0000000)// Overlap Area for Decoder (MP4/MPG/JPG): 0 ~ 399// MP4 Decoder Used: 400 bytes#define MP4_ROM_VARS_ADDR (REG_SRAM_BASE) // Size: CT909P - 28; CT909S - 32#define MP4_STATE_ROM_ADDR (REG_SRAM_BASE + 0x20) // Size: CT909P - 288; CT909S - 280#define B_DIR_MV_ADDR (REG_SRAM_BASE + 0x140) // Size: 80// MPG Decoder Used: 64 bytes#define MP2_INFO_VARS_ADDR (REG_SRAM_BASE) // Size: 52#define SLICE_VARS_ADDR (REG_SRAM_BASE + 0x34) // Size: 20// JPG Decoder Used: 0 bytes// Common Area: 400 ~ 1024#define REG_SRAM_PLAYMODE (*(volatile BYTE *)(REG_SRAM_BASE+0x190L))// watchdog counter#define REG_SRAM_WATCHDOG (*(volatile DWORD *)(REG_SRAM_BASE+0x194L))#define REG_SRAM_DISPLINE (*(volatile DWORD *)(REG_SRAM_BASE+0x198L))#ifdef CT909G_IC_SYSTEM#define VLD_UPKDATA_WIDTH (4)#endif#if defined(CT909R_IC_SYSTEM) || defined(CT909P_IC_SYSTEM)#define VLD_UPKDATA_WIDTH (3)#endif///////////////////////////////////////////////////////////////////////////////#define SHOW_BITS(N) (*(volatile DWORD *)(REG_VLD_BASE-4L+((BYTE)(N)<<2)))#define FLUSH_BITS(N) \{ \ REG_VLD_CTL = ((N<<VLD_NUM)|VLD_EXE); \}#ifdef __cplusplus }#endif#endif⌨️ 快捷键说明
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