ctkav_platform.h

ct952 source code use for Digital Frame Photo

// define PROM (Parallel/Serial Flash) registers
// -------------------------------------------------------------------------------------------------
#define REG_PLATFORM_PROM_BASE          (IO_START+0x2a00)                                           // 80002a00
// -------------------------------------------------------------------------------------------------
// define Parallel Flash Controller registers
#ifndef CT909G_IC_SYSTEM
    #define REG_PLAT_PROMCFG                (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x00)))   // 2a00 (909G: del)
    #ifndef CT909P_IC_SYSTEM
        #define REG_PLAT_KRAMADR                (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x04)))   // 2a04 (909G: del)
        #define REG_PLAT_KRAMDATA               (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x08)))   // 2a08 (909G: del)
        #define REG_PLAT_CRAMADR                (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x0c)))   // 2a0c (909G: del)
        #define REG_PLAT_CRAMDATAL              (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x10)))   // 2a10 (909G: del)
        #define REG_PLAT_CRAMDATAH              (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x14)))   // 2a14 (909G: del)
        #define REG_PLAT_CBADR                  (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x18)))   // 2a18 (909G: del)
        #define REG_PLAT_CBDATA                 (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x1c)))   // 2a1c (909G: del)
    #endif
#endif
// -------------------------------------------------------------------------------------------------
// define Serial (SPI) Flash Controller registers
#if defined(CT909P_IC_SYSTEM) || defined(CT909G_IC_SYSTEM)
    #define REG_PLAT_SPI_CMD                (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x24)))   // 2a24
    #define REG_PLAT_SPI_OP                 (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x28)))   // 2a28
    #define REG_PLAT_SPI_READ_TYPE          (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x2c)))   // 2a2c
    #define REG_PLAT_SPI_WRITE              (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x30)))   // 2a30
    #define REG_PLAT_SPI_READ               (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x34)))   // 2a34
    #define REG_PLAT_SPI_SCLK_CTRL          (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x38)))   // 2a38
#else
    #define REG_PLAT_SPI_CMD                (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x20)))   // 2a20
    #define REG_PLAT_SPI_OP                 (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x24)))   // 2a24
    #define REG_PLAT_SPI_READ_TYPE          (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x28)))   // 2a28
    #define REG_PLAT_SPI_WRITE              (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x2c)))   // 2a2c
    #define REG_PLAT_SPI_READ               (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x30)))   // 2a30
    #define REG_PLAT_SPI_SCLK_CTRL          (*((volatile DWORD *) (REG_PLATFORM_PROM_BASE+0x34)))   // 2a34
#endif
// =================================================================================================
// define register for External IO Config
#if !defined(CT909P_IC_SYSTEM) && !defined(CT909G_IC_SYSTEM)
    #define REG_PLAT_EXTIOCFG               (*((volatile DWORD *) (IO_START+0x2b00)))               // 2b00
#endif
// =================================================================================================
// define register for Write Protection
#ifdef CT909G_IC_SYSTEM
// -------------------------------------------------------------------------------------------------
    #define REG_PLATFORM_WPROT_BASE         (IO_START+0x2b00)                                       // 80002b00
// -------------------------------------------------------------------------------------------------
    #define REG_PLAT_PROC1_WPROT1_START     (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x00)))  // 2b00 (909G: new)
    #define REG_PLAT_PROC1_WPROT1_END       (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x04)))  // 2b04 (909G: new)
    #define REG_PLAT_PROC1_WPROT2_START     (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x08)))  // 2b08 (909G: new)
    #define REG_PLAT_PROC1_WPROT2_END       (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x0c)))  // 2b0c (909G: new)
    #define REG_PLAT_PROC2_WPROT1_START     (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x10)))  // 2b10 (909G: new)
    #define REG_PLAT_PROC2_WPROT1_END       (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x14)))  // 2b14 (909G: new)
    #define REG_PLAT_PROC2_WPROT2_START     (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x18)))  // 2b18 (909G: new)
    #define REG_PLAT_PROC2_WPROT2_END       (*((volatile DWORD *) (REG_PLATFORM_WPROT_BASE+0x1c)))  // 2b1c (909G: new)
#endif
// =================================================================================================
// define register for Panel Key Scan
// -------------------------------------------------------------------------------------------------
#define REG_PLATFORM_PANEL_BASE         (IO_START+0x2c00)                                       // 80002c00
// -------------------------------------------------------------------------------------------------
#define REG_PLAT_PANEL_CFG              (*((volatile DWORD *) (REG_PLATFORM_PANEL_BASE+0x00)))  // 2c00
#define REG_PLAT_PANEL_CLK              (*((volatile DWORD *) (REG_PLATFORM_PANEL_BASE+0x04)))  // 2c04
#define REG_PLAT_PANEL_DISP0            (*((volatile DWORD *) (REG_PLATFORM_PANEL_BASE+0x08)))  // 2c08
#define REG_PLAT_PANEL_KD               (*((volatile DWORD *) (REG_PLATFORM_PANEL_BASE+0x0c)))  // 2c0c
#define REG_PLAT_PANEL_INTCTRL          (*((volatile DWORD *) (REG_PLATFORM_PANEL_BASE+0x10)))  // 2c10
#define REG_PLAT_PANEL_INT              (*((volatile DWORD *) (REG_PLATFORM_PANEL_BASE+0x14)))  // 2c14
// =================================================================================================
// define DSU registers
// -------------------------------------------------------------------------------------------------
#define REG_PLATFORM_DSU_BASE           (0x90000000)                                                // 90000000
// -------------------------------------------------------------------------------------------------
#define REG_PLAT_DSU_CONTROL            (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x00)))        // 90000000
#define REG_PLAT_DSU_TRACE_BUF_CONTROL  (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x04)))        // 90000004
#define REG_PLAT_DSU_TIME_TAG_COUNTER   (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x08)))        // 90000008
#define REG_PLAT_DSU_AHB_BREAK_ADDR1    (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x10)))        // 90000010
#define REG_PLAT_DSU_AHB_MASK1          (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x14)))        // 90000014
#define REG_PLAT_DSU_AHB_BREAK_ADDR2    (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x18)))        // 90000018
#define REG_PLAT_DSU_AHB_MASK2          (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x1c)))        // 9000001c
#define REG_PLAT_DSU_O(n, m)            (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x20000+(((DWORD)64*(n)+32+4*(m))&(64*8-1)))))
#define REG_PLAT_DSU_L(n, m)            (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x20000+(((DWORD)64*(n)+64+4*(m))&(64*8-1)))))
#define REG_PLAT_DSU_I(n, m)            (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x20000+(((DWORD)64*(n)+96+4*(m))&(64*8-1)))))
#define REG_PLAT_DSU_G(n)               (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x20200+4*(n))))// 90020200
#define REG_PLAT_DSU_Y                  (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80000)))     // 90080000
#define REG_PLAT_DSU_PSR                (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80004)))     // 90080004
#define REG_PLAT_DSU_WIM                (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80008)))     // 90080008
#define REG_PLAT_DSU_TBR                (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x8000c)))     // 9008000c
#define REG_PLAT_DSU_PC                 (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80010)))     // 90080010
#define REG_PLAT_DSU_NPC                (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80014)))     // 90080014
#define REG_PLAT_DSU_FSR                (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80018)))     // 90080018
#define REG_PLAT_DSU_TRAP               (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x8001c)))     // 9008001c
#define REG_PLAT_DSU_ASR16              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80040)))     // 90080040
#define REG_PLAT_DSU_ASR17              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80044)))     // 90080044
#define REG_PLAT_DSU_ASR18              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80048)))     // 90080048
#define REG_PLAT_DSU_ASR19              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x8004c)))     // 9008004c
#define REG_PLAT_DSU_ASR20              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80050)))     // 90080050
#define REG_PLAT_DSU_ASR21              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80054)))     // 90080054
#define REG_PLAT_DSU_ASR22              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80058)))     // 90080058
#define REG_PLAT_DSU_ASR23              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x8005c)))     // 9008005c
#define REG_PLAT_DSU_ASR24              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80060)))     // 90080060
#define REG_PLAT_DSU_ASR25              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80064)))     // 90080064
#define REG_PLAT_DSU_ASR26              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80068)))     // 90080068
#define REG_PLAT_DSU_ASR27              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x8006c)))     // 9008006c
#define REG_PLAT_DSU_ASR28              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80070)))     // 90080070
#define REG_PLAT_DSU_ASR29              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80074)))     // 90080074
#define REG_PLAT_DSU_ASR30              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x80078)))     // 90080078
#define REG_PLAT_DSU_ASR31              (*((volatile DWORD *) (REG_PLATFORM_DSU_BASE+0x8007c)))     // 9008007c
// -------------------------------------------------------------------------------------------------
// -------------------------------------------------------------------------------------------------
// define DSU registers
// -------------------------------------------------------------------------------------------------
#define REG_PLATFORM_DSU2_BASE          (0x98000000)                                                // 98000000
// -------------------------------------------------------------------------------------------------
#define REG_PLAT_DSU2_CONTROL           (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x00)))       // 98000000
#define REG_PLAT_DSU2_TRACE_BUF_CONTROL (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x04)))       // 98000004
#define REG_PLAT_DSU2_TIME_TAG_COUNTER  (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x08)))       // 98000008
#define REG_PLAT_DSU2_AHB_BREAK_ADDR1   (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x10)))       // 98000010
#define REG_PLAT_DSU2_AHB_MASK1         (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x14)))       // 98000014
#define REG_PLAT_DSU2_AHB_BREAK_ADDR2   (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x18)))       // 98000018
#define REG_PLAT_DSU2_AHB_MASK2         (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x1c)))       // 9800001c
#define REG_PLAT_DSU2_O(n, m)           (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x20000+(((DWORD)64*(n)+32+4*(m))&(64*8-1)))))
#define REG_PLAT_DSU2_L(n, m)           (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x20000+(((DWORD)64*(n)+64+4*(m))&(64*8-1)))))
#define REG_PLAT_DSU2_I(n, m)           (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x20000+(((DWORD)64*(n)+96+4*(m))&(64*8-1)))))
#define REG_PLAT_DSU2_G(n)              (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x20200+4*(n))))// 90020200
#define REG_PLAT_DSU2_Y                 (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80000)))    // 98080000
#define REG_PLAT_DSU2_PSR               (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80004)))    // 98080004
#define REG_PLAT_DSU2_WIM               (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80008)))    // 98080008
#define REG_PLAT_DSU2_TBR               (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x8000c)))    // 9808000c
#define REG_PLAT_DSU2_PC                (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80010)))    // 98080010
#define REG_PLAT_DSU2_NPC               (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80014)))    // 98080014
#define REG_PLAT_DSU2_FSR               (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80018)))    // 98080018
#define REG_PLAT_DSU2_TRAP              (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x8001c)))    // 9808001c
#define REG_PLAT_DSU2_ASR16             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80040)))    // 98080040
#define REG_PLAT_DSU2_ASR17             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80044)))    // 98080044
#define REG_PLAT_DSU2_ASR18             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80048)))    // 98080048
#define REG_PLAT_DSU2_ASR19             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x8004c)))    // 9808004c
#define REG_PLAT_DSU2_ASR20             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80050)))    // 98080050
#define REG_PLAT_DSU2_ASR21             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80054)))    // 98080054
#define REG_PLAT_DSU2_ASR22             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80058)))    // 98080058
#define REG_PLAT_DSU2_ASR23             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x8005c)))    // 9808005c
#define REG_PLAT_DSU2_ASR24             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80060)))    // 98080060
#define REG_PLAT_DSU2_ASR25             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80064)))    // 98080064
#define REG_PLAT_DSU2_ASR26             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80068)))    // 98080068
#define REG_PLAT_DSU2_ASR27             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x8006c)))    // 9808006c
#define REG_PLAT_DSU2_ASR28             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80070)))    // 98080070
#define REG_PLAT_DSU2_ASR29             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80074)))    // 98080074
#define REG_PLAT_DSU2_ASR30             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x80078)))    // 98080078
#define REG_PLAT_DSU2_ASR31             (*((volatile DWORD *) (REG_PLATFORM_DSU2_BASE+0x8007c)))    // 9808007c
// =================================================================================================
// J500CSC_108, save code protection flag, text and rodata sections of PROC1 & PROC2,
// at following memory. Its mechanism is listed as follows.
// (1) Flash booting: BOOT code will update the correct setting to this address.
// (2) Its default setting is no protection at all, i.e. lower bits, 0-th and 1-th, are 0.
//     If the code is boot from memory, all code won't be protected.
// 0x40000005c is useless memory for trap window_overflow and its default value is
// 0x010000000, nop instruction.
// Here, we also treat PROC2 can be H/W reset if its code is protected.
// Joey: Because 0x4000005c is used by standard library (non-eCos), we change address from 0x4000005c to 0x4000008c,
//       and it's floating point exception.
#define PLAT_CODE_PROTECTION            (*((volatile DWORD *) (0x4000008c)))
#define PLAT_CODE_PROTECT_PROC1         (0x00000001)
#define PLAT_CODE_PROTECT_PROC2         (0x00000002)
#define SPARC_NOP_INSTRUCTION           (0x01000000)
// =================================================================================================
// define some global macros
#define PLAT_PROC1_DCACHE_DISABLE       (REG_PLAT_CACHE_CONTROL&=(~(CACHE_DCACHE_ENABLE|CACHE_DATA_BURST_FETCH)))
#define PLAT_PROC1_DCACHE_ENABLE        (REG_PLAT_CACHE_CONTROL|=(CACHE_DCACHE_ENABLE|CACHE_DATA_BURST_FETCH))
#define PLAT_PROC1_ICACHE_DISABLE       (REG_PLAT_CACHE_CONTROL&=(~(CACHE_ICACHE_ENABLE|CACHE_INSTRUCTION_BURST_FETCH)))
#define PLAT_PROC1_ICACHE_ENABLE        (REG_PLAT_CACHE_CONTROL|=(CACHE_ICACHE_ENABLE|CACHE_INSTRUCTION_BURST_FETCH))
#define PLAT_PROC1_CACHE_DISABLE        (REG_PLAT_CACHE_CONTROL&=(~(CACHE_DCACHE_ENABLE|CACHE_DATA_BURST_FETCH|CACHE_ICACHE_ENABLE|CACHE_INSTRUCTION_BURST_FETCH)))
#define PLAT_PROC1_CACHE_ENABLE         (REG_PLAT_CACHE_CONTROL|=(CACHE_DCACHE_ENABLE|CACHE_DATA_BURST_FETCH|CACHE_ICACHE_ENABLE|CACHE_INSTRUCTION_BURST_FETCH))
#define PLAT_PROC1_ICACHE_FLUSH         (REG_PLAT_CACHE_CONTROL|=(CACHE_FLUSH_ICACHE))