📄 ctkav_platform.h

📁 ct952 source code use for Digital Frame Photo
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#define INT_PROC1_2ND_MCU_OSDRD         (0x00000100)#define INT_PROC1_2ND_VBUF_OVERFLOW     (0x00000200)#define INT_PROC1_2ND_VBUF_UNDERFLOW    (0x00000400)#define INT_PROC1_2ND_ABUF_OVERFLOW     (0x00000800)#define INT_PROC1_2ND_SP1BUF_OVERFLOW   (0x00001000)#define INT_PROC1_2ND_SP2BUF_OVERFLOW   (0x00002000)#define INT_PROC1_2ND_STBBUF_OVERFLOW   (0x00004000)#define INT_PROC1_2ND_OSD_UNDERFLOW     (0x00008000)#define INT_PROC1_2ND_OSD_ERR           (0x00010000)#define INT_PROC1_2ND_MAIN_UNDER        (0x00020000)#define INT_PROC1_2ND_SP_ERR            (0x00040000)#define INT_PROC1_2ND_PLA_ERR           (0x00080000)#define INT_PROC1_2ND_MCU_WR_PROTECTION (0x00100000)#define INT_PROC1_2ND_VPU               (0x00200000)#define INT_PROC1_2ND_ERR_CNT           (0x00400000)#define INT_PROC1_2ND_PANEL_IR          (0x00800000)#ifdef CT909P_IC_SYSTEM    #define INT_PROC1_2ND_FCR               (0x01000000)  // 909P: new    #define INT_PROC1_2ND_NFC               (0x02000000)  // 909P: new#endif// -------------------------------------------------------------------------------------------------// define interrupt bit for INT_PROC2_1ST#define INT_PROC2_1ST_MIC_UNDERFLOW         (0x00000100)#define INT_PROC2_1ST_ABUF_UNPK0_UNDERFLOW  (0x00000200)#define INT_PROC2_1ST_ABUF_UNPK1_UNDERFLOW  (0x00000400)#define INT_PROC2_1ST_PCM_UNDERFLOW         (0x00000800)#define INT_PROC2_1ST_SPDIFOUT_UNDERFLOW    (0x00001000)#define INT_PROC2_1ST_PCM0_UNDERFLOW        (0x00002000)#define INT_PROC2_1ST_CLB                   (0x00004000)#define INT_PROC2_1ST_MCU_WR_PROTECTION     (0x00008000)// -------------------------------------------------------------------------------------------------// define INT default#define INT_SET_ALL                     (0xffffffff)#define INT_CLEAR_ALL                   (0x00000000)// -------------------------------------------------------------------------------------------------// -------------------------------------------------------------------------------------------------// define cache control bits#define CACHE_ICACHE_ENABLE             (0x00000003)#define CACHE_DCACHE_ENABLE             (0x0000000c)#define CACHE_FLUSH_DCACHE_PENDING      (0x00004000)#define CACHE_FLUSH_ICACHE_PENDING      (0x00008000)#define CACHE_INSTRUCTION_BURST_FETCH   (0x00010000)#define CACHE_DATA_BURST_FETCH          (0x00020000)#define CACHE_DCACHE_POWER_SAVING       (0x00040000)#define CACHE_FLUSH_ICACHE              (0x00200000)#define CACHE_FLUSH_DCACHE              (0x00400000)// -------------------------------------------------------------------------------------------------// -------------------------------------------------------------------------------------------------// define UART control bits#define UART_RX_ENABLE                  (0x00000001)#define UART_TX_ENABLE                  (0x00000002)#define UART_RX_INT_ENABLE              (0x00000004)#define UART_TX_INT_ENABLE              (0x00000008)#define UART_ODD_PARITY                 (0x00000010)#define UART_PARITY_ENABLE              (0x00000020)#define UART_FLOW_CONTROL               (0x00000040)#define UART_LOOP_BACK                  (0x00000080)// -------------------------------------------------------------------------------------------------// define UART status bits#define UART_STATUS_DATA_READY          (0x00000001)#define UART_STATUS_TS_EMPTY            (0x00000002)    // Transmitter shift (TS) register empty#define UART_STATUS_TH_EMPTY            (0x00000004)    // Transmitter hold (TH) register empty#define UART_STATUS_BREAK_RECEIVE       (0x00000008)#define UART_STATUS_OVERRUN             (0x00000010)#define UART_STATUS_PARITY_ERROR        (0x00000020)#define UART_STATUS_FRAME_ERROR         (0x00000040)// -------------------------------------------------------------------------------------------------typedef struct  tagUART_STRU{    DWORD   dwControl;    DWORD   dwScaler;} UART_STRU, *PUART_STRU;// =================================================================================================// define Clock Generator & Reset Controller registers// -------------------------------------------------------------------------------------------------#define REG_PLATFORM_RESET_CLOCK_BASE   (IO_START+0x300)                                                  // 80000300// -------------------------------------------------------------------------------------------------// define Clock Generator & Reset Controller registers#define REG_PLAT_CLK_GENERATOR_CONTROL  (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x00)))  // 0300#define REG_PLAT_RESET_CONTROL_DISABLE  (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x04)))  // 0304#define REG_PLAT_CLK_FREQ_CONTROL1      (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x08)))  // 0308#define REG_PLAT_MPLL_CONTROL           (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x10)))  // 0310#define REG_PLAT_APLL_CONTROL           (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x14)))  // 0314#ifndef CT909G_IC_SYSTEM    #define REG_PLAT_UPLL_CONTROL           (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x18)))  // 0318 (909G: del)#endif#define REG_PLAT_SYSTEM_CONFIGURATION1  (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x1c)))  // 031c#define REG_PLAT_SYSTEM_CONFIGURATION2  (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x20)))  // 0320#define REG_PLAT_RESET_CONTROL_ENABLE   (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x24)))  // 0324#ifdef CT909G_IC_SYSTEM    #define REG_PLAT_SYS_PIN_USE0           (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x28)))  // 0328 (909G: new)    #define REG_PLAT_SYS_PIN_USE1           (*((volatile DWORD *) (REG_PLATFORM_RESET_CLOCK_BASE+0x2c)))  // 032c (909G: new)#endif// -------------------------------------------------------------------------------------------------// -------------------------------------------------------------------------------------------------// define CLOCK Generator Gating Control bits for REG_PLAT_CLK_GENERATOR_CONTROL#define PLAT_MCLK_PROC2_DISABLE     (0x00000001)#define PLAT_MCLK2_AIU_DISABLE      (0x00000002)#define PLAT_MCLK2_BIU_DISABLE      (0x00000004)#define PLAT_MCLK_VDEC_DISABLE      (0x00000008)#define PLAT_MCLK2_VDEC_DISABLE     (0x00000010)#define PLAT_MCLK_DSU_DISABLE       (0x00000020)#define PLAT_MCLK2_SERVO_DISABLE    (0x00000040)#define PLAT_DSSPCLK_DISABLE        (0x00000080)#define PLAT_DCLK_DISABLE           (0x00000100)#define PLAT_DVDCLK_DISABLE         (0x00000200)#define PLAT_CDCLK_DISABLE          (0x00000400)#define PLAT_MCLK2_VOU_DISABLE      (0x00000800)#define PLAT_CLK27M_IR_DISABLE      (0x00001000)#ifndef CT909G_IC_SYSTEM    #define PLAT_MCLK2_DVDIF_DISABLE    (0x00002000)    // 909G: del#endif#define PLAT_MCLK2_VPU_DISABLE      (0x00004000)#define PLAT_MCLK_PROM_DISABLE      (0x00008000)#ifndef CT909G_IC_SYSTEM    #define PLAT_MCLK_ACP_DISABLE       (0x00010000)    // 909G: del#endif#define PLAT_TCLK_DISABLE           (0x00020000)#define PLAT_ACLK_DAC_DISABLE       (0x00040000)#define PLAT_BCLK_DAC_DISABLE       (0x00080000)#define PLAT_ACLK_ADC_DISABLE       (0x00100000)#define PLAT_BCLK_ADC_DISABLE       (0x00200000)#define PLAT_ACLK2_DAC_DISABLE      (0x00400000)#ifndef CT909G_IC_SYSTEM    #define PLAT_HCLK_USB_DISABLE       (0x00800000)    // 909G: del    #define PLAT_UCLK48M_USB_DISABLE    (0x01000000)    // 909G: del#endif#define PLAT_MCLK_VOU_DISABLE       (0x02000000)// -------------------------------------------------------------------------------------------------// -------------------------------------------------------------------------------------------------// define PLATFORM Reset Control Disable bits for REG_PLAT_RESET_CONTROL_DISABLE#define PLAT_RESET_PROC2_DISABLE        (0x00000001)#define PLAT_RESET_AIU_DISABLE          (0x00000002)#define PLAT_RESET_BIU_DISABLE          (0x00000004)#define PLAT_RESET_UART1_DISABLE        (0x00000008)#define PLAT_RESET_UART2_DISABLE        (0x00000010)#define PLAT_RESET_IRQ1_DISABLE         (0x00000020)#define PLAT_RESET_IRQ2_DISABLE         (0x00000040)#define PLAT_RESET_TIMER_DISABLE        (0x00000080)#define PLAT_RESET_VDEC_DISABLE         (0x00000100)#define PLAT_RESET_VDEC2_DISABLE        (0x00000200)#define PLAT_RESET_SERVO_DISABLE        (0x00000400)#define PLAT_RESET_DSSP_DISABLE         (0x00000800)#define PLAT_RESET_DVD_DISABLE          (0x00001000)#define PLAT_RESET_CD_DISABLE           (0x00002000)#define PLAT_RESET_ECC_DISABLE          (0x00004000)#define PLAT_RESET_DPLL_DISABLE         (0x00008000)#define PLAT_RESET_EDC_DISABLE          (0x00010000)#define PLAT_RESET_RF_DISABLE           (0x00020000)#define PLAT_RESET_DSU1_DISABLE         (0x00040000)#define PLAT_RESET_DSU2_DISABLE         (0x00080000)#define PLAT_RESET_VOU2_DISABLE         (0x00100000)#define PLAT_RESET_IR_DISABLE           (0x00200000)#ifndef CT909G_IC_SYSTEM    #define PLAT_RESET_DVDIF_DISABLE        (0x00400000)    // 909G: del#endif#define PLAT_RESET_VPU_DISABLE          (0x00800000)#define PLAT_RESET_PROM_DISABLE         (0x01000000)#ifndef CT909G_IC_SYSTEM    #define PLAT_RESET_ACP_DISABLE          (0x02000000)    // 909G: del    #define PLAT_RESET_USB_DISABLE          (0x04000000)    // 909G: del    #define PLAT_RESET_USBCLKCKT_DISABLE    (0x08000000)    // 909G: del#endif#define PLAT_RESET_VOU_DISABLE          (0x10000000)#if defined(CT909P_IC_SYSTEM) || defined(CT909G_IC_SYSTEM)    #define PLAT_RESET_AIU_DAC_DISABLE      (0x20000000)    // 909G: new#endif// -------------------------------------------------------------------------------------------------// define PLATFORM Reset Control Enable bits for REG_PLAT_RESET_CONTROL_ENABLE#define PLAT_RESET_PROC2_ENABLE         (0x00000001)
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