q6805_top.tf

q6805.zip

`timescale 1ns/1ns

// Q6805_TOP simple test fixture
// Version 1.01
// November 6, 2003
// QuickCores

module t;

reg CLK_2X;
wire CPU_CLK;
wire EClockStretch;
wire FLASH_CE_n;
wire [21:00] EXP_ADDRS;
wire [7:0] DB;
wire WR_n;
wire RD_n;
wire OPCOD_n;
wire FETCH_n;
wire IACK_n;
wire DISC_n;
reg RESET_n;
wire [7:0] PORTA;
wire [7:0] PORTB;
wire [7:0] PORTC;
wire TermA;
wire TermB;
wire SQWA;
wire SQWB;
wire SQWC;
wire TxD;
wire RxD;
wire OSC_EN;
reg TCK;
reg TDI;
wire TDO;
reg TMS;
reg TRST_n;

    Q6805_TOP m (
			
		    .CLK_2X(CLK_2X),				// 2X clock input from oscillator
		    .CPU_CLK(CPU_CLK),				// CPU clock output
		    .EClockStretch(EClockStretch),	// "stretched" E Clock
		    .FLASH_CE_n(FLASH_CE_n),		// active low chip enable for external flash
		    .EXP_ADDRS(EXP_ADDRS),			// expanded address -- up to 4 mega bytes
		    .DB(DB),						// bi-directional data bus
		    .WR_n(WR_n),					// active low write enable centered in the bus cycle by 1/4 CPU Clock
		    .RD_n(RD_n),					// active low read enable 1/4 clock after beginning of bus cycle

		    .OPCOD_n(OPCOD_n),				// active low op-code fetch (1st byte)
		    .FETCH_n(FETCH_n),				// active low fetch
		    .IACK_n(IACK_n),				// active low interrupt acknowledge
		    .DISC_n(DISC_n),				// active low discontinuity
		    .RESET_n(RESET_n),				// active low reset

		    .PORTA(PORTA),					// PORTA, 8-bits with programmable data direction
		    .PORTB(PORTB),					// PORTB, 8-bits with programmable data direction
		    .PORTC(PORTC),					// PORTB, 8-bits with programmable data direction and keyboard wake-up

			.TermA(TermA),					// active high terminal count for timer/counter A
			.TermB(TermB),					// active high terminal count for timer/counter B

			.SQWA(SQWA),					// timer/counter A squarewave output
			.SQWB(SQWB),					// timer/counter B squarewave output
			.SQWC(SQWC),					// timer/counter C squarewave output

			.TxD(TxD),						// asynchronous serial port transmit output
			.RxD(RxD),						// asynchronous serial port receive input

			.OSC_EN(OSC_EN),				// active high enable for oscillator

		    .TCK(TCK),						// JTAG TCK
		    .TDI(TDI),						// JTAG TDI
		    .TDO(TDO),						// JTAG TDO
		    .TMS(TMS),						// JTAG TMS
		    .TRST_n(TRST_n));

reg [7:0]	prog_mem[65535:0];				// define the program memory range
reg [15:0]	i;								// general purpose index



wire [15:0] RAM_ADDRS;
wire [7:0] RAM_DATA;

assign RAM_ADDRS = EXP_ADDRS[15:0];
assign RAM_DATA = prog_mem[RAM_ADDRS];

assign (pull1, pull0) RxD = TxD;

assign (pull1, pull0) DB = (~RD_n & ~FLASH_CE_n) ?  RAM_DATA : 8'hzz ;
assign (pull1, pull0) PORTA = 8'hFF;		// pull PORTA pins high
assign (pull1, pull0) PORTB = 8'hFF;		// pull PORTB pins high
assign (pull1, pull0) PORTC = 8'hFF;		// pull PORTC pins high
assign (pull1, pull0) TDO = 1'b1;			// pull TDO high

integer	clk_high_time;						// high time for CPU clock

initial
	begin

		i = 16'h0000;						// load external memory with nop's
		repeat (65536)
			begin
				prog_mem[i[15:0]] = 8'h9d;
				i = i + 1;
			end

		$readmemh("SINE_MOD.v",prog_mem);		// this example file contains the 6805 object code
											// that will be loaded into program memory
		clk_high_time = 12;					// the CPU clock period in nanoseconds is calculated as follows: 1/(4 * clk_high_time)
		RESET_n = 0;						// force reset low
		CLK_2X = 0;
		TRST_n = 0;
		TCK = 1'b1;
		TMS = 1'b1;
		TDI = 1'b1;
		#200
			RESET_n = 1;					// bring ready and reset high
#100000
$finish;
	end
	
		
always
	begin
		#clk_high_time 
			CLK_2X = ~CLK_2X;					   
	end


always @(posedge WR_n)
	begin
		if (~FLASH_CE_n) prog_mem[RAM_ADDRS] = DB;	 		// on the rising edge of WR_n moves contents
						 									// of the data bus to prog_mem pointed to
						 									// by address A
	end



endmodule // t