pio8wk.v

q6805.zip

																						
	module IOKey (  BlockSel,
			   		RegSel,
			   		CPUWR,
			   		CPUClock,
			   		IntRequest,
			   		IOPort,
			   		DIn,
			   		DOut,
			   		Reset,
			   		Ready);

	input 			BlockSel,
					CPUWR,
					CPUClock,
					Reset,
					Ready;

	inout [7:0] 	IOPort;
	input [1:0] 	RegSel;
	input [7:0] 	DIn;

	output [7:0] 	DOut;
	output		 	IntRequest;


	reg [7:0] DDR;
	reg [7:0] DReg;
	reg [7:0] KeyIFResetReg;
	reg [7:0] KeyIF;
	reg [7:0] KeyIE;

	reg [7:0] DOut;

	wire IntRequest =  ((KeyIF[7] & KeyIE[7]) |
					    (KeyIF[6] & KeyIE[6]) |
					    (KeyIF[5] & KeyIE[5]) |
					    (KeyIF[4] & KeyIE[4]) |
					    (KeyIF[3] & KeyIE[3]) |
					    (KeyIF[2] & KeyIE[2]) |
					    (KeyIF[1] & KeyIE[1]) |
					    (KeyIF[0] & KeyIE[0]));


	wire DRegSel  = BlockSel & (RegSel[1:0] == 2'b00) & Ready;
	wire DDRSel   = BlockSel & (RegSel[1:0] == 2'b01) & Ready;
	wire KeyIESel = BlockSel & (RegSel[1:0] == 2'b10) & Ready;
	wire KeyIFSel = BlockSel & (RegSel[1:0] == 2'b11) & Ready;

	wire [7:0] 	IOPort;									   // these are the actual pins
	wire [7:0]  DRegIn;

	wire DRegIn7_n = !DRegIn[7];
	wire DRegIn6_n = !DRegIn[6];
	wire DRegIn5_n = !DRegIn[5];
	wire DRegIn4_n = !DRegIn[4];
	wire DRegIn3_n = !DRegIn[3];
	wire DRegIn2_n = !DRegIn[2];
	wire DRegIn1_n = !DRegIn[1];
	wire DRegIn0_n = !DRegIn[0];
			   
	assign IOPort[7] = DDR[7] ? DReg[7] : 1'bz;
	assign IOPort[6] = DDR[6] ? DReg[6] : 1'bz;
	assign IOPort[5] = DDR[5] ? DReg[5] : 1'bz;
	assign IOPort[4] = DDR[4] ? DReg[4] : 1'bz;
	assign IOPort[3] = DDR[3] ? DReg[3] : 1'bz;
	assign IOPort[2] = DDR[2] ? DReg[2] : 1'bz;
	assign IOPort[1] = DDR[1] ? DReg[1] : 1'bz;
	assign IOPort[0] = DDR[0] ? DReg[0] : 1'bz;

	assign DRegIn = IOPort;
	
   
	always @(posedge CPUClock or posedge Reset) begin
		if (Reset)
			DDR[7:0] <= 8'h00;
		else begin
			if (DDRSel & CPUWR) begin
			   	DDR[7:0] <= DIn[7:0];
			end
		end
	end

	always @(posedge CPUClock or posedge Reset) begin
		if (Reset)
			DReg[7:0] <= 8'h00;
		else begin
			if (DRegSel & CPUWR) begin
			   	DReg[7:0] <= DIn[7:0];
			end
		end
	end

   
   always @(posedge CPUClock or posedge Reset) begin
		if (Reset)
			KeyIE[7:0] <= 8'h00;
		else begin
			if (KeyIESel & CPUWR) begin
			   	KeyIE[7:0] <= DIn[7:0];
			end
		end
	end



	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) begin
			KeyIFResetReg[7:0] <= 8'b1111_1111;
		end
		else begin
					if (KeyIF[7] & KeyIFSel & CPUWR) KeyIFResetReg[7] <= DIn[7];
					else KeyIFResetReg[7] <= 1'b0;	
							   
					if (KeyIF[6] & KeyIFSel & CPUWR) KeyIFResetReg[6] <= DIn[6];
					else KeyIFResetReg[6] <= 1'b0;	
							   
					if (KeyIF[5] & KeyIFSel & CPUWR) KeyIFResetReg[5] <= DIn[5];
					else KeyIFResetReg[5] <= 1'b0;	
							   
					if (KeyIF[4] & KeyIFSel & CPUWR) KeyIFResetReg[4] <= DIn[4];
					else KeyIFResetReg[4] <= 1'b0;	
							   
					if (KeyIF[3] & KeyIFSel & CPUWR) KeyIFResetReg[3] <= DIn[3];
					else KeyIFResetReg[3] <= 1'b0;	
							   
					if (KeyIF[2] & KeyIFSel & CPUWR) KeyIFResetReg[2] <= DIn[2];
					else KeyIFResetReg[2] <= 1'b0;	
							   
					if (KeyIF[1] & KeyIFSel & CPUWR) KeyIFResetReg[1] <= DIn[1];
					else KeyIFResetReg[1] <= 1'b0;	
							   
					if (KeyIF[0] & KeyIFSel & CPUWR) KeyIFResetReg[0] <= DIn[0];
					else KeyIFResetReg[0] <= 1'b0;			   
		end
	end
			
    always @(posedge DRegIn7_n or posedge KeyIFResetReg[7]) begin
		if (KeyIFResetReg[7])
    		KeyIF[7] <= 1'b0;
        else 
            KeyIF[7] <= 1'b1;
    end           

    always @(posedge DRegIn6_n or posedge KeyIFResetReg[6]) begin
		if (KeyIFResetReg[6])
    		KeyIF[6] <= 1'b0;
         else 
            KeyIF[6] <= 1'b1;
    end           

    always @(posedge  DRegIn5_n or posedge KeyIFResetReg[5]) begin
		if (KeyIFResetReg[5])
    		KeyIF[5] <= 1'b0;
        else 
            KeyIF[5] <= 1'b1;
    end           

    always @(posedge  DRegIn4_n or posedge KeyIFResetReg[4]) begin
		if (KeyIFResetReg[4])
    		KeyIF[4] <= 1'b0;
        else 
            KeyIF[4] <= 1'b1;
    end           

    always @(posedge  DRegIn3_n or posedge KeyIFResetReg[3]) begin
		if (KeyIFResetReg[3])
    		KeyIF[3] <= 1'b0;
        else 
            KeyIF[3] <= 1'b1;
    end           

    always @(posedge  DRegIn2_n or posedge KeyIFResetReg[2]) begin
		if (KeyIFResetReg[2])
    		KeyIF[2] <= 1'b0;
        else 
            KeyIF[2] <= 1'b1;
    end           

    always @(posedge  DRegIn1_n or posedge KeyIFResetReg[1]) begin
		if (KeyIFResetReg[1])
    		KeyIF[1] <= 1'b0;
        else 
            KeyIF[1] <= 1'b1;
    end           

    always @(posedge  DRegIn0_n or posedge KeyIFResetReg[0]) begin
		if (KeyIFResetReg[0])
    		KeyIF[0] <= 1'b0;
        else 
            KeyIF[0] <= 1'b1;
    end       
    
    
    always @(RegSel or DDR or DRegIn or KeyIE or KeyIF) begin
    	casex (RegSel)   
			2'b00 : DOut = DRegIn;
			2'b01 : DOut = DDR;
			2'b10 : DOut = KeyIE;
			2'b11 : DOut = KeyIF;
			default : DOut = 8'hxx;
		endcase
	end

endmodule	//IOKey