cntr8.v

q6805.zip

module	CNTR8( BlockSel,
			   RegSel,
			   CPURD,
			   CPUWR,
			   CPUClock,
			   Gate,
			   Trigger,
			   SquareWave,
			   TermCount,
			   IntRequest,
			   DIn,
			   DOut,
			   Reset,
			   Ready);



	input  BlockSel;
	input  RegSel;
	input  CPURD;
	input  CPUWR;
	input  CPUClock;
	input  Gate;
	input  Trigger;
	output SquareWave;
	output TermCount;
	output IntRequest;
	input  [7:0] DIn;
	output [7:0] DOut;
	input  Reset;
	input Ready;


	reg [7:0] ReloadValue;
	reg [6:1] ControlReg;
	reg SquareWave;
	reg TermCount;
	reg IntRequest;
	reg [7:0] DOut;
	reg [1:0] TriggerOS;

	reg [7:0] CurrentCount;


	wire CounterSel;
	wire ControlSel;

	wire TriggerPulse;

	wire CountEnable;
	wire IntEnable;
	wire TriggerEdge;
	wire ActiveLevel;
	wire AutoReload;
	wire TriggerActive;
	wire GateActive;
	wire [7:0] StatusReg;
	wire BaseSel;
	wire ZeroOrOne;
	wire LoadOrCount;
	wire LoadCounter;
	wire ReloadTheCounter;
	wire CountNow;
	wire TriggerMode;
	wire One;
	wire Zero;
	
	assign IntEnable    = ControlReg[6];
	assign CountEnable  = ControlReg[5];
	assign TriggerEdge  = ControlReg[4];
	assign ActiveLevel  = ControlReg[3];
	assign AutoReload   = ControlReg[2];
	assign TriggerMode  = ControlReg[1];

	assign StatusReg[7] = IntRequest;
	assign StatusReg [6:1] = ControlReg[6:1];
	assign StatusReg [0] = SquareWave;

	assign CounterSel = BlockSel & RegSel & Ready;
	assign ControlSel = BlockSel & !RegSel & Ready;

	assign TriggerActive = !(Trigger ^ TriggerEdge);
	assign GateActive = !(Gate ^ ActiveLevel);
	assign ZeroOrOne = !(|CurrentCount[7:1]);
	assign ReloadTheCounter = CountNow & ZeroOrOne & AutoReload;
	 
	assign LoadCounter = (CounterSel & CPUWR) ? 1'b1 : ReloadTheCounter;
												

	assign LoadOrCount = LoadCounter | CountEnable;

	assign CountNow = CountEnable & (TriggerMode ? (GateActive & TriggerPulse) : (GateActive | TriggerPulse));

	assign One = (CurrentCount == 8'h01);
	assign Zero = (CurrentCount == 8'h00);

	assign TriggerPulse = TriggerOS[1] & !TriggerOS[0];


	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) CurrentCount <= 8'h00;
		else begin
			if (LoadCounter) CurrentCount <= ReloadTheCounter ? ReloadValue : DIn;
			else if (CountNow) 	CurrentCount <= CurrentCount - 1'b1;
		end
	end
		
	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) begin
			ReloadValue  <= 8'h00;
			ControlReg	 <= 6'h00;
			SquareWave   <= 1'b0;
			TermCount    <= 1'b1;
		end
		else begin
			if (CounterSel & CPUWR) begin
				ReloadValue <= DIn;
			end
			if (ControlSel & CPUWR) begin
				ControlReg[6:1] <= DIn[6:1];
				if (DIn[0]) SquareWave <= !SquareWave;
			end
						
			if (~TermCount | (~|ReloadValue[7:0])) TermCount <= 1'b1;
			else if (CountNow & One) begin 
				TermCount <= 1'b0;
				SquareWave <= !SquareWave;
			end
			else if (CountNow & Zero & AutoReload) begin 
					TermCount <= 1'b0;
					SquareWave <= !SquareWave;
			end
		end
	end
	
	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) begin
			IntRequest <= 1'b0;
		end
		else begin
			if (CountNow & ZeroOrOne) IntRequest <= IntEnable;
		    else if (IntRequest & ControlSel & CPURD) IntRequest <= 1'b0;
		end
	end	
	
	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) begin
			TriggerOS <= 2'b0;
		end
		else begin
			TriggerOS[1] <= Trigger;
			TriggerOS[0] <= TriggerOS[1];
		end
	end

					 
	always @( CounterSel  or ControlSel or CurrentCount  or StatusReg) begin
		if (CounterSel) DOut = CurrentCount;
		else  DOut = StatusReg;
	end
			
			
endmodule