debug.v

q6805.zip

assign ZERO_OR_ONE = (CNTR_VAL[7:1] == 7'b0) & EVNT_EN;

always @(posedge TCK or posedge TRST) begin
	if (TRST) begin
		CNTR_DR <= 'b0;
	end
	else begin
		if (SEL_EVNT_CNTR & UPDAT_DR) begin
			CNTR_DR <= D;
		end
	end
end

always @(posedge CPU_CLK or posedge TRST) begin
	if (TRST) begin
		CNTR_VAL <= 'b0;
	end
	else if (EVNT_EN) begin
		
		if (ZERO_OR_ONE) begin
			CNTR_VAL <= CNTR_DR;
		end
		else begin
			CNTR_VAL <= CNTR_VAL - 1'b1;
		end
   end
end


always @(posedge XCLK_L) begin
	Latch_Sync <= !LTCH_CNTR;
end


always @(Latch_Sync or CNTR_VAL or EVNT_CNT_VAL) begin
	if(Latch_Sync) begin
		EVNT_CNT_VAL = CNTR_VAL;
	end
	else begin
		EVNT_CNT_VAL = EVNT_CNT_VAL;
	end
end

always @(CNTR_DR or CNTR_VAL or EVNT_EN) begin
	if (CNTR_DR == 8'h01) begin
		CNTR_EVNT = EVNT_EN;
	end
	else begin
		CNTR_EVNT = (CNTR_VAL == 8'h02) & EVNT_EN;
	end
end


endmodule // evnt_cnt


module disc_stk( 
				BRK_IN_SRVC, 
				BRK_PND, 
				CLR_STK, 
				CNTR_EVNT, 
				CPU_CLK, 
				CPU_DISCNTY,
             	CPU_FRST_W, 
             	CPU_PC, 
             	CPU_RDY, 
             	D, 
             	DISABL_STK, 
             	DSTK_OUT,
             	DSTK_SEL, 
             	EVNT_EN, 
             	LTCH_CNTR, 
             	RESET, 
             	SEL_EVNT_CNTR, 
             	TCK,
            	UPDAT_DR, 
            	XCLK_L );

input BRK_IN_SRVC; 
input BRK_PND; 
input CLR_STK;
output CNTR_EVNT;
input CPU_CLK; 
input CPU_DISCNTY; 
input CPU_FRST_W;
input [15:0] CPU_PC;
input CPU_RDY;
input [7:0] D;
input DISABL_STK;
output [7:0] DSTK_OUT;
input [3:0] DSTK_SEL;
input EVNT_EN; 
input LTCH_CNTR; 
input RESET; 
input SEL_EVNT_CNTR; 
input TCK; 
input UPDAT_DR; 
input XCLK_L;


reg BufReset;
reg Stack_Enable;
reg [1:0] PUSH;

reg	[15:0] PC_Reg;
reg	[15:0] DSTK_A;
reg	[15:0] DSTK_B;
reg	[15:0] DSTK_C;
reg [7:0]  DSTK_OUT;


wire PUSH_2;
wire Capture_PC;
wire [7:0] ECV;
wire [7:0] CNTR_DR;


assign PUSH_2 = Stack_Enable & (|PUSH[1:0]) & CPU_RDY & !BRK_IN_SRVC;
assign Capture_PC = Stack_Enable & CPU_RDY & CPU_FRST_W & !(BRK_PND | BRK_IN_SRVC);

evnt_cnt evnt_cnt1 ( .CNTR_DR({ CNTR_DR[7:0] }), .CNTR_EVNT(CNTR_EVNT),
             .CPU_CLK(CPU_CLK), .D({ D[7:0] }), .EVNT_CNT_VAL({ ECV[7:0] }),
             .EVNT_EN(EVNT_EN), .LTCH_CNTR(LTCH_CNTR),
             .SEL_EVNT_CNTR(SEL_EVNT_CNTR), .TCK(TCK), .TRST(RESET),
             .UPDAT_DR(UPDAT_DR), .XCLK_L(XCLK_L) );


always @(posedge CPU_CLK) begin						// this block synchronizes JTAG control signals
	BufReset <= RESET | CLR_STK;					// to the CPU clock
	Stack_Enable <= !DISABL_STK;
	if(CPU_RDY) begin
		PUSH[0] <= CPU_DISCNTY & !BRK_IN_SRVC;		// this is a one-shot for generating a PUSH signal
		PUSH[1] <= PUSH[0];							// the push is two cycles long (two pushes)
	end
end

always @(posedge CPU_CLK or posedge BufReset) begin
	if (BufReset) begin
		PC_Reg <= 16'h0000;							// clear trace buffer to 0
		DSTK_A <= 16'h0000;
		DSTK_B <= 16'h0000;
		DSTK_C <= 16'h0000;
	end
	else begin
		if (Capture_PC) begin						// anytime there is an opcode fetch and the buffer is
			PC_Reg <= CPU_PC;						// enabled, then capture the PC
		end
		if (PUSH_2) begin						   	// the PUSH_2 signal is two cycles long and everyone is 
			DSTK_A <= PC_Reg;					   	// pushed twice if there is a discontinuity and the 
			DSTK_B <= DSTK_A;					   	// buffer is enabled
			DSTK_C <= DSTK_B;
		end
	end
end

always @(DSTK_A or DSTK_B or DSTK_C or PC_Reg or ECV or CNTR_DR or DSTK_SEL) begin
	case (DSTK_SEL[3:0])
		4'b0000 : DSTK_OUT = DSTK_A[7:0];
		4'b0001 : DSTK_OUT = DSTK_A[15:8];
		4'b0010 : DSTK_OUT = DSTK_B[7:0];
		4'b0011 : DSTK_OUT = DSTK_B[15:8];
		4'b0100 : DSTK_OUT = DSTK_C[7:0];
		4'b0101 : DSTK_OUT = DSTK_C[15:8];
		4'b0110 : DSTK_OUT = PC_Reg[7:0];
		4'b0111 : DSTK_OUT = PC_Reg[15:8];
		4'b1000 : DSTK_OUT = ECV[7:0];
		4'b1100 : DSTK_OUT = CNTR_DR[7:0];
		default : DSTK_OUT = 'bx;
	endcase
end

endmodule // disc_stk


module debug( BREAK, BRK_CMPLT, BRK_IN_SRVC, BRK_PND, BRK_REQ, CLR_MFUNC, CNTR_EVNT,
             CPU_CLK, CPU_DISC, CPU_FRST_WRD, CPU_FTCH, CPU_PC, CPU_RD,
             CPU_RDY, CPU_RESET, CPU_STOP, CPU_WAIT, CPU_WR, DB, EVNT0_IN,
             EXT_RESET_IN, IACKq, MFUNC_CMPLT, MFUNC_REQ, MON_ADR, MON_DAT,
             MON_EXC, MON_IN_SRVC, MON_OPCD, MSR_CMPLT, STK_PTR, TCK, TDI,
             TDO, TDO_OE, TMS, XCLK_L, XTCK, XTRST);

output BREAK;
input BRK_CMPLT, BRK_IN_SRVC, BRK_PND;
output BRK_REQ, CLR_MFUNC, CNTR_EVNT;
input CPU_CLK, CPU_DISC, CPU_FRST_WRD, CPU_FTCH;
input [15:0] CPU_PC;
input CPU_RD, CPU_RDY;
output CPU_RESET;
input CPU_STOP, CPU_WAIT, CPU_WR;
input [7:0] DB;
input EVNT0_IN, EXT_RESET_IN, IACKq, MFUNC_CMPLT;
output MFUNC_REQ;
output [15:0] MON_ADR;
output [7:0] MON_DAT;
input MON_EXC, MON_IN_SRVC;
output [7:0] MON_OPCD;
input MSR_CMPLT;
input [7:0] STK_PTR;
input TCK, TDI;
output TDO, TDO_OE;
input TMS, XCLK_L, XTCK, XTRST;

reg [7:0] CNTRL;
reg [7:0] MON_DB;
reg [7:0] STAK_PTR;
reg       TDO;


wire [7:0] STATUS;
wire [7:0] SHFTR;
wire [15:0] Y;
wire [7:0] IR;
wire [7:0] DSTK;
wire [15:0] CMPR;
wire [4:0] CYCL_EN;
wire SHIFT_IR;
wire SHIFT_DR;
wire CLOCK_DR;
wire CLOCK_IR;
wire J_RESET;
wire UPDAT_DR;
wire SEL_BYP;
wire SELECT;
wire SOUT_IR;
wire SOUT_DR;
wire SOUT_BYP;
wire EVNT_TERM_CNT;
wire EVNT_DET;
wire BRK_REQq;
wire CPU_RESET;
wire CNTR_EVNT;
wire CLR_MFUNC;
wire BRK_REQ;
wire BREAK;
wire UPDATE_IR;
wire FETCH1;
wire IACK1;
wire WRQ1;

wire J_RESETo;
wire FRST_WORD_OR_CPU_RESET;

assign CPU_RESET = EXT_RESET_IN | CNTRL[0];
assign CNTR_EVNT = XCLK_L & EVNT_TERM_CNT;
assign CLR_MFUNC = UPDAT_DR & Y[12];
assign BRK_REQ   = XCLK_L & BRK_REQq;
assign BREAK     = BRK_PND | BRK_IN_SRVC | BRK_REQ;

assign FRST_WORD_OR_CPU_RESET = CPU_RESET | CPU_FRST_WRD;

assign J_RESET = J_RESETo;

disc_stk disc_stk ( 
		.BRK_IN_SRVC(BRK_IN_SRVC), 
		.BRK_PND(BRK_PND),
      	.CLR_STK(CNTRL[5]), 
      	.CNTR_EVNT(EVNT_TERM_CNT), 
      	.CPU_CLK(CPU_CLK),
        .CPU_DISCNTY(CPU_DISC), 
        .CPU_FRST_W(FRST_WORD_OR_CPU_RESET),
        .CPU_PC({ CPU_PC[15:0] }), 
        .CPU_RDY(CPU_RDY),
        .D({ SHFTR[7:0] }), 
        .DISABL_STK(CNTRL[6]),
        .DSTK_OUT({ DSTK[7:0] }), 
        .DSTK_SEL({ IR[3:0] }),
        .EVNT_EN(EVNT_DET), 
        .LTCH_CNTR(CNTRL[4]), 
        .RESET(J_RESET),
        .SEL_EVNT_CNTR(Y[13]), 
        .TCK(TCK), 
        .UPDAT_DR(UPDAT_DR),
        .XCLK_L(XCLK_L) );

jtg_stat jtg_stat ( 
		.STAT0(BRK_IN_SRVC), 
		.STAT1(BRK_CMPLT), 
		.STAT2(CPU_STOP),
        .STAT3(CPU_WAIT), 
        .STAT4(CPU_RESET), 
        .STAT5(MON_IN_SRVC),
        .STAT6(MSR_CMPLT), 
        .STAT7(MFUNC_CMPLT), 
        .STATUS({ STATUS[7:0] }) );

j_regs j_regs ( 
		.CMPR_H({ CMPR[15:8] }), 
		.CMPR_L({ CMPR[7:0] }),
        .CYCL({ CYCL_EN[4:0] }), 
        .JRESET(J_RESET),
        .MFUNC_CMPLT(MFUNC_CMPLT), 
        .MFUNC_REQ(MFUNC_REQ),
        .MON_ADR({ MON_ADR[15:0] }), 
        .MON_DAT({ MON_DAT[7:0] }),
        .MON_OPCD({ MON_OPCD[7:0] }), 
        .SEL_CMPR_H(Y[5]),
        .SEL_CMPR_L(Y[4]), 
        .SEL_CYCTYP(Y[8]), 
        .SEL_MON_ADRH(Y[3]),
        .SEL_MON_ADRL(Y[2]), 
        .SEL_MON_DAT(Y[7]), 
        .SEL_MON_OPCD(Y[6]),
        .SHFTR({ SHFTR[7:0] }), 
        .TCK(TCK), 
        .UPDAT_DR(UPDAT_DR) );

jtag_brk jtag_brk ( 
		.BRK_IN_SRVC(BRK_IN_SRVC), 
		.BRK_REQ(BRK_REQq), 
		.CMPR({ CMPR[15:0] }),
        .CPU_CLK(CPU_CLK), 
        .CPU_RDY(CPU_RDY), 
        .CPU_RESET(J_RESET),
        .CYC_TYP({ CYCL_EN[4:0] }), 
        .EN_BRK(CNTRL[2]),
        .EN_EXT_BRK(CNTRL[3]), 
        .EVNT0(EVNT0_IN), 
        .EVNT_CNT(EVNT_TERM_CNT),
        .EVNT_DET(EVNT_DET), 
        .FETCH(CPU_FTCH), 
        .FRC_BRK(CNTRL[1]),
        .FRST_WRD(CPU_FRST_WRD), 
        .IACKq(IACKq), 
        .MFUNC(MON_EXC),
        .PC({ CPU_PC[15:0] }), 
        .RD(CPU_RD), 
        .WR(CPU_WR) );

jtag_byp jtag_byp ( 
		.BYP_SEL(SEL_BYP), 
		.SHIFT_DR(SHIFT_DR), 
		.SIN(TDI), 
		.SOUT(SOUT_BYP),
        .TCK(TCK) );

jtgshft8 jtgshft8 ( 
		.A({ MON_DB[7:0] }), 
		.B({ STAK_PTR[7:0] }), 
		.C({ STATUS[7:0] }),
        .D({ DSTK[7:0] }), 
        .EN_CLOCK_DR(CLOCK_DR), 
        .SEL0(Y[11]), 
        .SEL1(Y[12]),
        .SHFTR({ SHFTR[7:0] }), 
        .SHIFT_DR(SHIFT_DR), 
        .SI(TDI), 
        .SO(SOUT_DR),
        .TCK(TCK) );

jtag_ir jtag_ir ( 
		.IR_Q({ IR[7:0] }), 
		.RESET(J_RESET), 
		.SEL_IR(CLOCK_IR),
        .SHIFT_IR(SHIFT_IR), 
        .SIN(TDI), 
        .SOUT(SOUT_IR), 
        .TCK(TCK),
        .UPDATE_IR(UPDATE_IR) );

jtag_dec jtag_dec ( 
		.A({ IR[4:0] }), 
		.SEL_BYP(SEL_BYP), 
		.Y({ Y[15:0] }) );

tap tap ( .CLOCK_DR(CLOCK_DR), 
		.CLOCK_IR(CLOCK_IR), 
		.ENABLE(TDO_OE), 
		.RESET(J_RESETo),
        .SELECT(SELECT), 
        .SHIFT_DR(SHIFT_DR), 
        .SHIFT_IR(SHIFT_IR), 
        .TCK(TCK),
        .TMS(TMS), 
        .UPDATE_DR(UPDAT_DR), 
        .UPDATE_IR(UPDATE_IR), 
        .XTCK(XTCK),
        .XTRST(XTRST) );


always @(posedge TCK or posedge J_RESET) begin
	if(J_RESET) begin
		CNTRL <= 'b0;
	end
	else begin
		if (UPDAT_DR & Y[9]) begin
			CNTRL <= SHFTR;
		end
	end
end

always @(posedge CPU_CLK or posedge J_RESET) begin
	if (J_RESET) begin
		MON_DB   <= 'b0;
		STAK_PTR <= 'b0;
	end
	else begin
		if (CPU_RDY & MON_EXC) begin
			MON_DB <= DB;
		end
		if (CPU_RDY & !BRK_IN_SRVC) begin
			STAK_PTR <= STK_PTR;
		end
	end
end	

always @(posedge XTCK) begin
	TDO <= SELECT ? SOUT_IR : (SEL_BYP ? SOUT_BYP : SOUT_DR);
end							 

endmodule // jtag