debug.v

q6805.zip

module tap( CLOCK_DR, CLOCK_IR, ENABLE, RESET, SELECT, SHIFT_DR, SHIFT_IR, TCK, TMS,
            UPDATE_DR, UPDATE_IR, XTCK, XTRST );


output CLOCK_DR, CLOCK_IR, ENABLE, RESET, SELECT, SHIFT_DR, SHIFT_IR;
input TCK, TMS;
output UPDATE_DR, UPDATE_IR;
input XTCK, XTRST;

reg [3:0] TAP;
reg RESET;
reg ENABLE;
reg SHIFT_IRq;
reg SHIFT_DRq;
reg CLOCK_IRq;
reg UPDATE_IR;
reg CLOCK_DRq;
reg UPDATE_DR;


wire SELECT;
wire SHIFT_IR;
wire SHIFT_DR;
wire CLOCK_IR;
wire CLOCK_DR;
wire TRST;

assign SELECT = TAP[0];
assign SHIFT_IR = !SHIFT_IRq;
assign SHIFT_DR = !SHIFT_DRq;
assign CLOCK_IR = !CLOCK_IRq;
assign CLOCK_DR = !CLOCK_DRq;

assign TRST = !XTRST;

always @(posedge TCK or posedge TRST) begin
	if (TRST) begin
		TAP[3:0] <= 4'b1111;
	end
	else begin
		TAP[3] <= !(!(TAP[3] & !TAP[1] & !TMS)   		& 
				    !(TMS & !TAP[2])               		& 
				    !(TMS & !TAP[3])               		& 
				    !(TAP[1] & TAP[0] & TMS));

		TAP[2] <= !(!(TAP[2] & !TAP[3] & !TMS)   		& 
				    !(!TAP[1] & !TMS)              		& 
				    !(TAP[2] & !TAP[0] & !TMS)     		& 
				    !(!TAP[3] & !TAP[0] & !TMS)    		& 
				    !(TAP[1] & TMS & !TAP[2])      		& 
				    !(TAP[3] & TAP[1] & TAP[0] & TMS));

		TAP[1] <= !(!(TAP[1] & !TAP[2]) 				& 
				    !(TAP[3] & TAP[1]) 					& 
				    !(TMS & !TAP[2]));

		TAP[0] <= !(!(TAP[0] & !TAP[1]) 				& 
				    !(TAP[2] & TAP[0]) 					& 
				    !(TAP[1] & !TAP[2] & !TMS) 			& 
				    !(TAP[1] & !TAP[3] & !TAP[2] & !TAP[0]));
	end
end

always @(posedge XTCK or posedge TRST) begin
	if (TRST) begin
		RESET <= 1'b1;
		ENABLE <= 1'b0;
		SHIFT_IRq <= 1'b0;
		SHIFT_DRq <= 1'b0;
		CLOCK_IRq <= 1'b1;
		CLOCK_DRq <= 1'b1;	
		UPDATE_IR <= 1'b0;
		UPDATE_DR <= 1'b0;
	end
	else begin
		RESET <= &TAP[3:0];
		ENABLE <= !(!(TAP[2] & TAP[0] & !TAP[3] & !TAP[1]) 		& 
					!(TAP[2] & !TAP[3] & !TAP[1] & !TAP[0]));

		SHIFT_IRq <= !(TAP[2] & TAP[0] & !TAP[3] & !TAP[1]);

		SHIFT_DRq <= !(TAP[2] & !TAP[3] & !TAP[1] & !TAP[0]);

		CLOCK_IRq <= !(TAP[2] & TAP[0] & !TAP[3]);

		CLOCK_DRq <= !(TAP[2] & !TAP[3] & !TAP[0]);

		UPDATE_IR <= TAP[3] & TAP[1] & TAP[0] & !TAP[2];
		UPDATE_DR <= TAP[3] & !TAP[2] & TAP[1] & !TAP[0];

	end
end




endmodule // tap


module j_regs( CMPR_H, CMPR_L, CYCL, JRESET, MFUNC_CMPLT, MFUNC_REQ, MON_ADR,
               MON_DAT, MON_OPCD, SEL_CMPR_H, SEL_CMPR_L, SEL_CYCTYP,
               SEL_MON_ADRH, SEL_MON_ADRL, SEL_MON_DAT, SEL_MON_OPCD, SHFTR,
               TCK, UPDAT_DR );

output [15:8] CMPR_H;
output [7:0] CMPR_L;
output [4:0] CYCL;
input JRESET, MFUNC_CMPLT;
output MFUNC_REQ;
output [15:0] MON_ADR;
output [7:0] MON_DAT;
output [7:0] MON_OPCD;
input SEL_CMPR_H, SEL_CMPR_L, SEL_CYCTYP, SEL_MON_ADRH, SEL_MON_ADRL,SEL_MON_DAT, SEL_MON_OPCD;
input [7:0] SHFTR;
input TCK, UPDAT_DR;

reg [15:0] MON_ADR;
reg [7:0]  MON_DAT;
reg [7:0]  MON_OPCD;
reg [15:8]  CMPR_H;
reg [7:0]  CMPR_L;
reg [4:0]  CYCL;
reg 	   MFUNC_REQ;

wire TCK;
wire CLR_MFUNC_REQ;

assign CLR_MFUNC_REQ = JRESET | MFUNC_CMPLT;

always @(posedge TCK or posedge JRESET) begin
	if (JRESET) begin
		CYCL <= 5'b00000;
	end
	else begin
		if (UPDAT_DR & SEL_MON_ADRH) MON_ADR[15:8] <= SHFTR[7:0];
		if (UPDAT_DR & SEL_MON_ADRL) MON_ADR[7:0]  <= SHFTR[7:0];
		if (UPDAT_DR & SEL_MON_DAT)  MON_DAT[7:0]  <= SHFTR[7:0];
		if (UPDAT_DR & SEL_MON_OPCD) MON_OPCD[7:0] <= SHFTR[7:0];
		if (UPDAT_DR & SEL_CMPR_H)   CMPR_H[15:8]   <= SHFTR[7:0];
		if (UPDAT_DR & SEL_CMPR_L)   CMPR_L[7:0]   <= SHFTR[7:0];
		if (UPDAT_DR & SEL_CYCTYP)   CYCL[4:0]     <= SHFTR[4:0];
	end
end

always @(posedge TCK or posedge CLR_MFUNC_REQ) begin
	if (CLR_MFUNC_REQ) begin
		MFUNC_REQ <= 1'b0;
	end
	else begin
		if (UPDAT_DR & SEL_MON_DAT) begin
			MFUNC_REQ <= 1'b1;
		end
	end
end



endmodule // j_regs


module jtg_stat( STAT0, STAT1, STAT2, STAT3, STAT4, STAT5, STAT6, STAT7, STATUS );


input STAT0, STAT1, STAT2, STAT3, STAT4, STAT5, STAT6, STAT7;
output [7:0] STATUS;

wire [7:0] STATUS;

assign STATUS[7] = STAT7;
assign STATUS[6] = STAT6;
assign STATUS[5] = STAT5;
assign STATUS[4] = STAT4;
assign STATUS[3] = STAT3;
assign STATUS[2] = STAT2;
assign STATUS[1] = STAT1;
assign STATUS[0] = STAT0;


endmodule // jtg_stat


module jtgshft8( A, B, C, D, EN_CLOCK_DR, SEL0, SEL1, SHFTR, SHIFT_DR, SI, SO, TCK );

input [7:0] A;
input [7:0] B;
input [7:0] C;
input [7:0] D;
input EN_CLOCK_DR, SEL0, SEL1;
output [7:0] SHFTR;
input SHIFT_DR, SI;
output SO;
input TCK;


wire SO;
wire [7:0] D_SHFT_MUX;
wire [1:0] SELECT;

reg [7:0] SHFTR;


assign D_SHFT_MUX[7] = SHIFT_DR ?       SI : D[7];
assign D_SHFT_MUX[6] = SHIFT_DR ? SHFTR[7] : D[6];
assign D_SHFT_MUX[5] = SHIFT_DR ? SHFTR[6] : D[5];
assign D_SHFT_MUX[4] = SHIFT_DR ? SHFTR[5] : D[4];
assign D_SHFT_MUX[3] = SHIFT_DR ? SHFTR[4] : D[3];
assign D_SHFT_MUX[2] = SHIFT_DR ? SHFTR[3] : D[2];
assign D_SHFT_MUX[1] = SHIFT_DR ? SHFTR[2] : D[1];
assign D_SHFT_MUX[0] = SHIFT_DR ? SHFTR[1] : D[0];
 
assign SO = SHFTR[0];

assign SELECT[1:0] = {(SEL1 | SHIFT_DR), (SEL0 | SHIFT_DR)};

always @(posedge TCK) begin
	if (EN_CLOCK_DR | SHIFT_DR) begin
		case (SELECT[1:0])
			2'b00 : SHFTR <= A;
			2'b01 : SHFTR <= B;
			2'b10 : SHFTR <= C;
			2'b11 : SHFTR <= D_SHFT_MUX;
		endcase
	end
end


endmodule // jtgshft8


module jtag_ir( IR_Q, RESET, SEL_IR, SHIFT_IR, SIN, SOUT, TCK, UPDATE_IR );

output [7:0] IR_Q;
input RESET, SEL_IR, SHIFT_IR, SIN;
output SOUT;
input TCK, UPDATE_IR;


reg [7:0]	IR_SHIFT_REG;
reg [7:0]	IR_Q;

wire [7:0] IR_D_MUX;

wire SOUT;

assign SOUT = IR_SHIFT_REG[0];

assign IR_D_MUX = SHIFT_IR ? {SIN, IR_SHIFT_REG[7:1]} : 8'h01;

always @(posedge TCK or posedge RESET) begin
	if (RESET) begin
		IR_Q <= 8'h01;
	end
	else begin
		if (UPDATE_IR) begin
			IR_Q <= IR_SHIFT_REG;
		end
	end
end


always @(posedge TCK) begin
	if (SEL_IR | SHIFT_IR) begin
		IR_SHIFT_REG <= IR_D_MUX;
	end
end


endmodule // jtag_ir


module jtag_dec( A, SEL_BYP, Y );
 input [4:0] A;
output SEL_BYP;
 output [15:0] Y;

wire [15:0] Y;
wire SEL_BYP;

assign Y[15] = (A[4:0] == 5'h0F);
assign Y[14] = (A[4:0] == 5'h0E);
assign Y[13] = (A[4:0] == 5'h0D);
assign Y[12] = ((A[4:0] == 5'h0C) | A[4]);
assign Y[11] = ((A[4:0] == 5'h0B) | A[4]);
assign Y[10] = (A[4:0] == 5'h0A);
assign Y[9] = (A[4:0] == 5'h09);
assign Y[8] = (A[4:0] == 5'h08);
assign Y[7] = (A[4:0] == 5'h07);
assign Y[6] = (A[4:0] == 5'h06);
assign Y[5] = (A[4:0] == 5'h05);
assign Y[4] = (A[4:0] == 5'h04);
assign Y[3] = (A[4:0] == 5'h03);
assign Y[2] = (A[4:0] == 5'h02);
assign Y[1] = (A[4:0] == 5'h01);
assign Y[0] = (A[4:0] == 5'h00);

assign SEL_BYP = Y[15] | Y[14] | Y[1] | Y[0] | (Y[15] & A[4]);


endmodule // jtag_dec


module jtag_byp( BYP_SEL, SHIFT_DR, SIN, SOUT, TCK );

input BYP_SEL, SHIFT_DR, SIN;
output SOUT;
input TCK;

reg SOUT;

always @(posedge TCK) begin
	if (BYP_SEL) begin
		SOUT <= SHIFT_DR ? SIN : 1'b0;
	end
end



endmodule // jtag_byp


module jtag_brk( BRK_IN_SRVC, BRK_REQ, CMPR, CPU_CLK, CPU_RDY, CPU_RESET, CYC_TYP,
                 EN_BRK, EN_EXT_BRK, EVNT0, EVNT_CNT, EVNT_DET, FETCH,
                 FRC_BRK, FRST_WRD, IACKq, MFUNC, PC, RD, WR );

input BRK_IN_SRVC;
output BRK_REQ;
input [15:0] CMPR;
input CPU_CLK, CPU_RDY, CPU_RESET;
input [4:0] CYC_TYP;
input EN_BRK, EN_EXT_BRK, EVNT0, EVNT_CNT;
output EVNT_DET;
input FETCH, FRC_BRK, FRST_WRD, IACKq, MFUNC;
input [15:0] PC;
input RD, WR;

reg [1:0] Ext_Brk_Trig;
reg 	  Single_Step;

wire EVNT_DET;
wire BRK_REQ;



assign EVNT_DET = (((RD & CYC_TYP[3] & !FETCH   & !MFUNC)  | 
					        (WR & CYC_TYP[2]    & !MFUNC)  |
						    (FETCH & CYC_TYP[1] & !MFUNC)  |
						    (IACKq & CYC_TYP[0] & !MFUNC)) 
						&
						    (CYC_TYP[4] | (!(PC[15:0] ^ CMPR[15:0]))))
				|
						(Ext_Brk_Trig[0] &	!Ext_Brk_Trig[1]);

assign BRK_REQ = Single_Step | (EN_BRK & EVNT_CNT);


always @(posedge CPU_CLK or posedge CPU_RESET) begin
	if (CPU_RESET) begin
		Single_Step <= 1'b0;
	end
	else begin
		Ext_Brk_Trig[0] <= EN_EXT_BRK & !EVNT0;
		Ext_Brk_Trig[1] <= Ext_Brk_Trig[0];
		if (CPU_RDY) begin
			Single_Step <= FRST_WRD & FRC_BRK & !BRK_IN_SRVC;
		end
	end
end	 



endmodule // jtag_brk



module evnt_cnt( 
				CNTR_DR, 
				CNTR_EVNT, 
				CPU_CLK, 
				D, 
				EVNT_CNT_VAL, 
				EVNT_EN, 
				LTCH_CNTR,
                SEL_EVNT_CNTR, 
                TCK, 
                TRST, 
                UPDAT_DR, 
                XCLK_L );

output [7:0] CNTR_DR;
output 		 CNTR_EVNT;
input 		 CPU_CLK;
input  [7:0] D;
output [7:0] EVNT_CNT_VAL;
input 		 EVNT_EN; 
input 		 LTCH_CNTR; 
input 		 SEL_EVNT_CNTR; 
input 		 TCK; 
input 		 TRST; 
input 		 UPDAT_DR; 
input 		 XCLK_L;



wire ZERO_OR_ONE;

reg CNTR_EVNT;

reg [7:0] CNTR_DR;
reg [7:0] CNTR_VAL;
reg Latch_Sync;

reg [7:0] EVNT_CNT_VAL;