sci8dr.v

q6805.zip

module SCI8db (BlockSel,
			   RegSel,
			   CPURD,
			   CPUWR,
			   CPUClock,
			   IntRequest,
			   TxD,
			   RxD,
			   Baudx16,
			   DIn,
			   DOut,
			   Reset,
			   Ready);

	input 	BlockSel,
			CPURD,
			CPUWR,
			CPUClock,
			RxD,
			Baudx16,
			Reset,
			Ready;

	input 	RegSel;
	input 	[7:0] DIn;

	output	IntRequest,
			TxD;

	output	[7:0] DOut;

	reg [2:0] HalfBit;
	reg	RxDStartDetect;
	reg [3:0] RxDClock;
	reg [3:0] TxDClock;
	reg [3:0] RxDBitCount;
	reg [3:0] TxDBitCount;
	reg [8:0] RxDReg;
	reg [7:0] RDRBuf;
	reg [7:0] TxDReg;
	reg RxDFull;
	reg RxDShifting;
	reg TxDShifting;
	reg TxD;
	reg TxDBit;
	reg [7:0] DOut;

	
	reg TDRE;
	reg TxDEnable; 
	reg TIE;
	reg BRK;
	reg RDRF;
	reg	RDRF_Sync;
	reg RIE;
	reg RxDEnable; 
	reg FE;
	reg OverRunDetect;
	reg OE;
	reg OEPipe;

	wire ControlRegSel = 	(RegSel == 1'b0) & BlockSel & Ready;
	wire DataRegSel = 		(RegSel == 1'b1) & BlockSel & Ready;
	wire NineBitsShifted;
	wire StartBit;
	wire [7:0] StatusReg;
	wire IntRequest = ((TIE & TDRE) | (RIE & RDRF));

	assign StatusReg[7] = TDRE;
	assign StatusReg[6] = TIE;
	assign StatusReg[5] = OE;
	assign StatusReg[4] = BRK;
	assign StatusReg[3] = RDRF;
	assign StatusReg[2] = RIE;
	assign StatusReg[1] = RxDEnable;
	assign StatusReg[0] = FE;


	assign NineBitsShifted = (RxDBitCount == 4'b1001);
	assign StartBit = !TxDShifting;		 		

	always @(posedge Baudx16 or posedge Reset) begin
		if (Reset) begin
			HalfBit <= 3'b0;
			RxDStartDetect <= 1'b0;
			RxDShifting <= 1'b0;
			RxDClock <= 4'b0;
			RxDFull <= 1'b0;
			OverRunDetect <= 1'b0;
		end
		else begin
			RDRF_Sync <= !RDRF & RxDFull;
			if (!RxDEnable) begin
				HalfBit <= 3'b0;
				RxDShifting <= 1'b0;
				RxDStartDetect <= 1'b0;
			end

			if (RxDEnable & !RxDFull & !RxD & !RxDShifting) begin
			   	RxDStartDetect <= 1'b1;
			end
			else begin
				RxDStartDetect <= 1'b0;
			end
				
			if(RxDStartDetect & !RxDShifting) begin
				HalfBit <= HalfBit + 1'b1;
			end
			else begin
				HalfBit <= 3'b0;
			end

			if ( HalfBit[2:0] == 3'h6 ) RxDShifting <= 1'b1;
														  
			if ( RxDShifting ) begin
				RxDClock <= RxDClock + 1'b1;	
			end
			else begin
				RxDClock <= 4'b0;
			end
			if (NineBitsShifted) begin
				RxDFull <= 1'b1;
				RxDShifting <= 1'b0;
			end
			if (!RDRF & RxDFull) RxDFull <= 1'b0;

			if (RxDFull & !RxD) begin
				OverRunDetect <= 1'b1;
			end
			if (OEPipe) begin
				OverRunDetect <= 1'b0;
			end
			
		end
	end

	always @(posedge Baudx16 or posedge Reset) begin
		if (Reset) begin
			RxDBitCount <= 4'b0;
 			RxDReg <= 9'b0;
		end
		else begin
			if (RxDShifting & (&RxDClock[3:0])) begin

				RxDBitCount <= RxDBitCount + 1'b1;

				RxDReg <= {RxD, RxDReg[8:1]};

			end
			if( !RxDShifting) begin
				RxDBitCount <= 4'b0;
			end
		end
	end

	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) begin
			TxDReg    <= 1'b0;

			TDRE      <= 1'b1;
			TIE       <= 1'b0;
			TxDEnable <= 1'b0;
			BRK		  <= 1'b0;
			RDRF 	  <= 1'b0;
			RIE		  <= 1'b0;
			RxDEnable <= 1'b0;
			FE   	  <= 1'b0;
			OE		  <= 1'b0;
		end
		else begin
			if (!RxDEnable) begin
				RDRF <= 1'b0;
				FE   <= 1'b0;
				OE   <= 1'b0;
				OEPipe <= 1'b0;
			end

			if (RxDEnable & RDRF_Sync) begin
				RDRF <= 1'b1;
				FE   <= !RxDReg[8];
				RDRBuf[7:0] <= RxDReg[7:0];
				OEPipe <= OverRunDetect;
				OE <= OEPipe;

			end
		    if (RDRF & CPURD & DataRegSel) begin
				RDRF <= 1'b0;
			end
			if (FE & CPURD & DataRegSel) begin
				FE <= 1'b0;
			end
			if (OE & CPURD & DataRegSel) begin
				OE   <= 1'b0;
			end
			if (ControlRegSel & CPUWR) begin
				TIE 	  <= DIn[6];
				TxDEnable <= 1'b1;
				BRK 	  <= DIn[4];
				RIE		  <= DIn[2];
				RxDEnable <= DIn[1];
			end
			if (TDRE & CPUWR & DataRegSel) begin
				TxDReg <= DIn;	
				TDRE <= 1'b0;
			end
			if (TxDBitCount == 4'b1010) begin
				TDRE <= 1'b1;
			end
		end
	end


	// transmit section


	always @(posedge Baudx16 or posedge Reset) begin
		if (Reset) begin
			TxDClock <= 4'b0;
			TxDShifting <= 1'b0;
			TxD <= 1'b1;
		end
		else begin
			TxDShifting <= TxDEnable & !TDRE;
			if ( TxDShifting ) begin
				TxDClock <= TxDClock + 1'b1;
			end
			else begin
				TxDClock <= 4'b0;
			end
			TxD <= BRK ? 1'b0 : TxDBit;
	   	end
	end
	
	always @(posedge Baudx16 or posedge Reset) begin
		if (Reset) begin
			TxDBitCount <= 4'b0;
		end
		else begin
			if (TxDShifting & ( &TxDClock[3:0])) begin
				TxDBitCount <= TxDBitCount + 1'b1;
  			end
			if (!TxDShifting) begin
				TxDBitCount <= 4'h0;
			end
		end
	end								   		 	
	
	always @(TxDBitCount or TxDReg or StartBit) begin
		casex (TxDBitCount)
			4'h0 : TxDBit = StartBit;
			4'h1 : TxDBit = TxDReg[0];
			4'h2 : TxDBit = TxDReg[1];
			4'h3 : TxDBit = TxDReg[2];
			4'h4 : TxDBit = TxDReg[3];
			4'h5 : TxDBit = TxDReg[4];
			4'h6 : TxDBit = TxDReg[5];
			4'h7 : TxDBit = TxDReg[6];
			4'h8 : TxDBit = TxDReg[7];
			4'h9 : TxDBit = 1'b1;
			default : TxDBit = 1'b1;
	   	endcase
	end
	always @(RegSel or RDRBuf or StatusReg) begin
		case (RegSel)
			1'b0 : DOut = StatusReg;
			1'b1 : DOut = RDRBuf;
		endcase
	end

endmodule	//SCI8db