q6805_top.v

q6805.zip

		PIOB_ADRS  	: RD_INTRNL = PIOB_D;
		PIOWK_ADRS 	: RD_INTRNL = PIOWK_D;
		CNTRA_ADRS 	: RD_INTRNL = CNTRA_D;
		CNTRB_ADRS 	: RD_INTRNL = CNTRB_D;
		CNTRC_ADRS 	: RD_INTRNL = CNTRC_D;
		SCIA_ADRS  	: RD_INTRNL = SCIA_D;
		EXPWN_ADRS 	: RD_INTRNL = EXPWN_D;
		default  	: RD_INTRNL = RAM1_D;
	endcase
end


//
// Q6805 CPU instatntiation
//

Q6805_CPU CPU( 
			.CLK_2Xi(CLK_2X),
			.CLK_2Xo(),
			.CPU_CLK(CPU_CLK),
			.WClockp(WClockp),
			.EClock(),
			.EClock_n(),
			.EClockStretch(EClockStretch),
			.CPU_PC(CPU_PC),
			.RD_D(RD_D),
			.WR_D(WR_D),
			.WR_n(WR_n),
			.WRDELq(WRDELq),
			.WRQ1(WRQ1),	
			.RD_n(RD_n),
			.RDQ1(RDQ1),
			.OPCOD_n(OPCOD_n),
			.FETCH_n(FETCH_n),
			.IACK_n(IACK_n),
			.DISC_n(DISC_n),
			.INT(INT),
			.ACC(ACC),
			.XREG(XREG),
			.CCR(CCR),
			.PROD(PROD),
			.VECTOR(VECTOR),
			.STACK_BASE(STACK_BASE),
			.STK_PTR(),
			.WAITNG_n(),
			.STOPD_n(),
			.RESET_n(RESET_n),
			.RESET(RESET),
			.READY(EXP_RDY),
			.CPU_RDY(CPU_RDY),
			.MULE(1'b0),
			.TCK(TCK),
			.TDI(TDI),
			.TDO(TDO),
			.TMS(TMS),
			.TRST_n(TRST_n),
			.EVNT0_n(EVNT0_n),
			.EVNT1_n(EVNT1_n) );

// 
// example QuickLogic 4K RAM block instantiation -- remove comments enable
//
r4096a8_25um RAM1(
			.wa(CPU_PC[11:0]),
			.ra(CPU_PC[11:0]),
			.wd(WR_D),
			.rd(RAM1_D),
			.we(WRQ1 & RAM1_SEL),
			.wclk(CPU_CLK));

//
// example Actel ProASIC-PLUS 4K RAM block instatntiation -- remove comments to enable
//
//ram4kx8 RAM1(
//               .DO(RAM1_D), 
//               .WCLOCK(CPU_CLK), 
//               .DI(WR_D), 
//               .WRB(~(WRQ1 & RAM1_SEL)), 
//               .RDB(1'b0), 
//               .WADDR({CPU_PC[11:0]}), 
//               .RADDR({CPU_PC[11:0]}));

//
// example ALTERA Quartus II 4K RAM block instatntiation -- remove comments to enable
//
//ram4kx8 RAM1(
//				.data(WR_D),
//				.wren(WRQ1 & RAM1_SEL),
//				.wraddress({CPU_PC[11:0]}),
//				.rdaddress({CPU_PC[11:0]}),
//				.wrclock(CPU_CLK),
//				.rdclock(CLK_2X),
//				.q(RAM1_D));



//
// 8-bit PIO PORTA instantiation
//

PIO8 PIOA(  
			.BlockSel(PIOA_SEL),
			.RegSel(CPU_PC[0]),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.IOPort(PORTA),
			.DIn(WR_D),
			.DOut(PIOA_D),
			.Reset(RESET),
			.Ready(READY));

//
// 8-bit PIO PORTB instantiation
//

PIO8 PIOB(  
			.BlockSel(PIOB_SEL),
			.RegSel(CPU_PC[0]),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.IOPort(PORTB),
			.DIn(WR_D),
			.DOut(PIOB_D),
			.Reset(RESET),
			.Ready(READY));

//
// 8-bit PIO PORTC with edge detection keyboard wake-up instantiation
// can be programmed to generate an interrupt (lowest priority)
//

IOKey PIOWK(  
			.BlockSel(PIOWK_SEL),
			.RegSel(CPU_PC[1:0]),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.IntRequest(INT[0]),
			.IOPort(PORTC),
			.DIn(WR_D),
			.DOut(PIOWK_D),
			.Reset(RESET),
			.Ready(READY));

// 
// 8-bit programmable timer/counter	 A
// interrupt connected to IRQ3
//

CNTR8 CNTRA( 
			.BlockSel(CNTRA_SEL),
			.RegSel(CPU_PC[0]),
			.CPURD(RDQ1),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.Gate(GateA),
			.Trigger(TrigA),
			.SquareWave(SQWA),
			.TermCount(TermA),
			.IntRequest(INT[3]),
			.DIn(WR_D),
			.DOut(CNTRA_D),
			.Reset(RESET),
			.Ready(READY));

// 
// 8-bit programmable timer/counter	 B
// interrupt connected to IRQ2
//

CNTR8 CNTRB( 
			.BlockSel(CNTRB_SEL),
			.RegSel(CPU_PC[0]),
			.CPURD(RDQ1),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.Gate(GateB),
			.Trigger(TrigB),
			.SquareWave(SQWB),
			.TermCount(TermB),
			.IntRequest(INT[2]),
			.DIn(WR_D),
			.DOut(CNTRB_D),
			.Reset(RESET),
			.Ready(READY));

// 
// 8-bit programmable timer/counter	 C
// the terminal count signal of this timer/counter is used for baud rate generation
// no interrupts are required since operating in auto-reload mode, so not connected
//

CNTR8 CNTRC( 
			.BlockSel(CNTRC_SEL),
			.RegSel(CPU_PC[0]),
			.CPURD(RDQ1),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.Gate(GateC),
			.Trigger(TrigC),
			.SquareWave(SQWC),
			.TermCount(TermC),
			.IntRequest(),
			.DIn(WR_D),
			.DOut(CNTRC_D),
			.Reset(RESET),
			.Ready(READY));


//
// simple asynchronous serial port A
// interrupt connected to IRQ1
//

SCI8db SCIA(  
			.BlockSel(SCIA_SEL),
			.RegSel(CPU_PC[0]),
			.CPURD(RDQ1),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.IntRequest(INT[1]),
			.TxD(TxD),
			.RxD(RxD),
			.Baudx16(TermC),
			.DIn(WR_D),
			.DOut(SCIA_D),
			.Reset(RESET),
			.Ready(READY));

//
// memory address expander
// allows up to 2 mega bytes of program memory and 2 mega bytes data memory for a total of 4 megabytes
//

ExpWin ExpWin( 
			.BlockSel(EXPWN_SEL),
			.RegSel(CPU_PC[1:0]),
			.INTRNL_ADDRS(INTRNL_ADDRS),
			.CPUWR(WRDELq),
			.CPURD(~RD_n),
			.CPUClock(CPU_CLK), 
			.EClockStretch(EClockStretch),
			.NotWClock(~WClockp),
			.AddrsIn(CPU_PC),
			.AddrsOutQ(EXP_ADDRS),
			.CSP0_n(CSP0_n),
			.CSP1_n(CSP1_n),
			.CSD0_n(CSD0_n),
			.CSD1_n(CSD1_n),
			.CS3_n(),
			.CS2_n(),
			.CS1_n(),
			.CS0_n(),
			.DIn(WR_D),
			.WaitReqQ(EXP_RDY),
			.DOut(EXPWN_D),
			.Reset(RESET),
			.Ready(READY));

//
// Burr-Brown DAC7512 serial controller	channel A
//

DAC7512 DAC_A (
			.BlockSel(DAC_A_SEL),
			.RegSel(CPU_PC[0]),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.DIn(WR_D),
			.SYNC_n(SYNC_A_n),
			.SIn(SIn_A),
			.TxD_OE(),
			.Reset(RESET));

//
// Burr-Brown DAC7512 serial controller	channel B
//

DAC7512 DAC_B (
			.BlockSel(DAC_B_SEL),
			.RegSel(CPU_PC[0]),
			.CPUWR(WRQ1),
			.CPUClock(CPU_CLK),
			.DIn(WR_D),
			.SYNC_n(SYNC_B_n),
			.SIn(SIn_B),
			.TxD_OE(),
			.Reset(RESET));


 endmodule // Q6805_TOP