q6805_top.v

q6805.zip

//-----------------------------------------------------------------------------------------------------------------------
//
//	QuickCores Q6805 CPU example top-level design with on-chip JTAG debug and real-time monitoring
//  Version 1.02
//	November 06, 2003
//  
//	For updates and app-notes, development hardware, visit www.quickcores.com 
//  For technical assistance, call QuickCores at [phone] or send an email to [e-mail]
//
//
//	QuickCores has posted this Q6805 CPU netlist library for your unrestricted use and modification	with the hope that
//  	it may be useful, but QuickCores makes no warranty or guarantee (implied or otherwise) that it is free from 
//		errors or that it is fit for any purpose or that such use will not infringe the rights of anyone.  
//		QuickCores expressly disclaims any liability which may arise in whole 
//		or in part from its use or misuse including infringing the rights of anyone.  The posting of this
//		file or any related files is not intended to place into the public domain any related patents.
//
//  This is an example top-level Q6805 design with the following features:
//		(3) 8-bit parallel I/O ports (PORTA, PORTB and PORTC) with programmable data direction register
//		    PORTC also includes an 8-bit edge detection function (keyboard wake-up) which can be	programmed to
//			generate an interrupt on a falling edge of an enabled port bit
//		(3) 8-bit programmable timer/counter circuits.  Note that timer/counter C is used for baud rate generation
//		(1) simple asynchronous serial port
//		(1) memory extended address circuit with programmable wait-state generator can be used to extend the 
//			physical address reach to 4 megabytes.  Ideal for interfacing to >64K flash and RAM memory devices
//		(2) DAC7512 synchronous serial ports
//
//	The example design also includes the on-chip, real-time monitor and debug logic	module which is compatible
//		with Domain Technologies high level C language debugger and mini-USB JTAG controller pod 
//
//
//  Included in the .zip file is example C source code (targeted to ByteCraft LTD. C6805 C compiler) which  
//		documents the memory - I/O map
//
//	Also included in the .zip file is a preliminary design guide which explains the operation of the various peripherals
//		the peripherals are provided in original Verilog RTL but are not guaranteed to be free from errors
//
//	The design should easily synthesize with Symplify Lite (Actel, QuickLogic, Xilinx) and ALTERA Quartus II web edition)
//		Before synthesis, be sure to remove comments in front of the desired RAM block (see RAM instantiations below)
//		Depending on how you have your system configured, you may need to manually instantiate global clock buffers for 
//		CPU_CLK, TCK, BaudX16
//
//	If you need target hardware, QuickCores offers a project board with ALTERA Cyclone EP1C6T144C8 installed.
//	The board has dual 12-bit DACs, external flash memory, LCD, and built-in USB 1.1 programmer
//	The $500 price include BoxView high level C language debugger
//	For details, visit QuickCores web site at:  www.quickcores.com or email or call using information above.
//		
//-----------------------------------------------------------------------------------------------------------------------



module Q6805_TOP (
		    CLK_2X,				// 2X clock input from oscillator
		    CPU_CLK,			// CPU clock output
		    EClockStretch,		// "stretched" E Clock
		    FLASH_CE_n,			// active low chip enable for external flash
		    EXP_ADDRS,			// expanded address -- up to 4 mega bytes
		    DB,					// bi-directional data bus
		    WR_n,				// active low write enable centered in the bus cycle by 1/4 CPU Clock
		    RD_n,				// active low read enable 1/4 clock after beginning of bus cycle

		    OPCOD_n,			// active low op-code fetch (1st byte)
		    FETCH_n,			// active low fetch
		    IACK_n,				// active low interrupt acknowledge
		    DISC_n,				// active low discontinuity
		    RESET_n,			// active low reset

		    PORTA,				// PORTA, 8-bits with programmable data direction
		    PORTB,				// PORTB, 8-bits with programmable data direction
		    PORTC,				// PORTB, 8-bits with programmable data direction and keyboard wake-up

			TermA,				// active high terminal count for timer/counter A
			TermB,				// active high terminal count for timer/counter B

			SQWA,				// timer/counter A squarewave output
			SQWB,				// timer/counter B squarewave output
			SQWC,				// timer/counter C squarewave output

			TxD,				// asynchronous serial port transmit output
			RxD,				// asynchronous serial port receive input

			SYNC_A_n,			// sync output to DAC channel A	 sync input
			SYNC_B_n,			// sync output to DAC channel B	 sync input
			SIn_A,				// SIn (output) to DAC channel A serial input
			SIn_B,				// SIn (output) to DAC channel B serial input
			SCLK_A,				// SCLK to DAC channel A sclk input
			SCLK_B,				// SCLK to DAC channel B sclk input

			OSC_EN,				// active high enable for oscillator

		    TCK,				// JTAG TCK
		    TDI,				// JTAG TDI
		    TDO,				// JTAG TDO
		    TMS,				// JTAG TMS
		    TRST_n);			// JTAG TRST


input CLK_2X;			
output CPU_CLK;		
output EClockStretch;	
output FLASH_CE_n;		
output [21:00] EXP_ADDRS;		
output [7:0] DB;				
output WR_n;			
output RD_n;			

output OPCOD_n;		
output FETCH_n;		
output IACK_n;			
output DISC_n;			
input RESET_n;		

inout [7:0] PORTA;			
inout [7:0] PORTB;			
inout [7:0] PORTC;			

output TermA;			
output TermB;			

output SQWA;		
output SQWB;			
output SQWC;			

output TxD;		
input RxD;		

output SYNC_A_n;			
output SYNC_B_n;			
output SIn_A;		
output SIn_B;				
output SCLK_A;				
output SCLK_B;				

output OSC_EN;			

input TCK;			
input TDI;			
output TDO;			
input TMS;			
input TRST_n;		



parameter PIOA_ADRS  = 16'b0000_0000_0000_000x;
parameter PIOB_ADRS  = 16'b0000_0000_0000_001X;
parameter PIOWK_ADRS = 16'b0000_0000_0000_01xx;
parameter CNTRA_ADRS = 16'b0000_0000_0000_100x;
parameter CNTRB_ADRS = 16'b0000_0000_0000_101x;
parameter CNTRC_ADRS = 16'b0000_0000_0000_110x;
parameter SCIA_ADRS  = 16'b0000_0000_0000_111x;
parameter EXPWN_ADRS = 16'b0000_0000_0001_00xx;
parameter DAC_A_ADRS = 16'b0000_0000_0001_010x;
parameter DAC_B_ADRS = 16'b0000_0000_0001_011x;
parameter RAM1_ADRS  = 16'b0000_xxxx_xxxx_xxxx;

reg [7:0] RD_INTRNL;

//
// 8-bit data busses defined
//

wire [7:0] PORTA;
wire [7:0] PORTB;
wire [7:0] PORTC;
wire [7:0] PIOA_D;
wire [7:0] PIOB_D;
wire [7:0] PIOWK_D;
wire [7:0] CNTRA_D;
wire [7:0] CNTRB_D;
wire [7:0] CNTRC_D;
wire [7:0] SCIA_D;
wire [7:0] EXPWN_D;
wire [7:0] RAM1_D;
wire [7:0] DB;


wire [7:0]  ACC;					// accumulator contents
wire [15:0] XREG;					// X register contents
wire [7:0]  CCR;					// condition code regsiter contents
wire [15:0] PROD;					// result of external 8 X 8 multiply
wire [15:5] VECTOR;					// vector base
wire [15:6] STACK_BASE;				// stack base

wire [5:0] INT;						// six interrupts (only 4 are used here)

wire FLASH_CE_n;		
wire [7:0] DB;			
wire [7:0] RD_D;		
wire [7:0] WR_D;		

wire PIOA_SEL; 
wire PIOB_SEL; 
wire PIOWK_SEL;	 
wire CNTRA_SEL;
wire CNTRB_SEL;
wire CNTRC_SEL;
wire SCIA_SEL; 
wire DAC_A_SEL;
wire DAC_B_SEL;
wire EXPWN_SEL;
wire RAM1_SEL;

wire EXP_RDY;
wire READY;
wire RESET;
wire [21:0] EXP_ADDRS;
wire [15:0] CPU_PC;
wire CSP0_n;
wire CSP1_n;
wire CSD0_n;
wire CSD1_n;
wire EClockStretch;
wire RD_n;
wire WR_n;
wire OPCOD_n;
wire FETCH_n;
wire IACK_n;
wire DISC_n;
wire EVNT0_n;
wire EVNT1_n;
wire CPU_CLK;
wire WClockp;
wire WRDELq;
wire WRQ1;
wire OSC_EN;
wire INTRNL_ADDRS;


wire GateA;
wire GateB;
wire GateC;
wire TrigA;
wire TrigB;
wire TrigC;
wire TermA;
wire TermB;
wire TermC;
wire SQWA;
wire SQWB;
wire SQWV;

wire TxD;
																// Timer/counter A gate input tied low
assign GateA = 1'b0;											// Timer/counter B gate input tied low
assign GateB = 1'b0;											// Timer/counter C gate input tied low
assign GateC = 1'b0;											
																// Timer/counter A trigger input tied low
assign TrigA = 1'b0;											// Timer/counter B trigger input tied low
assign TrigB = 1'b0;											// Timer/counter C trigger input tied low
assign TrigC = 1'b0;

assign VECTOR = 11'b1111_1111_111;
assign STACK_BASE = 12'b0000_0000_0011;
assign INT[5:4] = 2'b00;
assign READY = 1'b1;
assign PROD = ACC * XREG;										// 8 X 8 H/W multiplier
assign OSC_EN = 1'b1;											// my application board requires that the external
																// oscillator be enabled with "1";

assign  FLASH_CE_n = ~((~CSP0_n | ~CSP1_n | ~CSD0_n | ~CSD1_n));// I'm ORing this together because in my application
																// I've only one Flash device
																// also note that in this application, there are 4K bytes
																// of internal RAM and I/O -- they have the highest priority

assign DB = (WRQ1 & ~FLASH_CE_n) ? WR_D :  8'hzz;				// data bus control

assign RD_D = (|CPU_PC[15:12]) ? DB : RD_INTRNL; 				// if address is > 4K then external read

assign PIOA_SEL  = (PIOA_ADRS[15:1]  == CPU_PC[15:1]);
assign PIOB_SEL  = (PIOB_ADRS[15:1]  == CPU_PC[15:1]);
assign PIOWK_SEL = (PIOWK_ADRS[15:2] == CPU_PC[15:2]);
assign CNTRA_SEL = (CNTRA_ADRS[15:1] == CPU_PC[15:1]);
assign CNTRB_SEL = (CNTRB_ADRS[15:1] == CPU_PC[15:1]);
assign CNTRC_SEL = (CNTRC_ADRS[15:1] == CPU_PC[15:1]);
assign SCIA_SEL  = (SCIA_ADRS[15:1]  == CPU_PC[15:1]);
assign EXPWN_SEL = (EXPWN_ADRS[15:2] == CPU_PC[15:2]);
assign DAC_A_SEL = (DAC_A_ADRS[15:1] == CPU_PC[15:1]);
assign DAC_B_SEL = (DAC_B_ADRS[15:1] == CPU_PC[15:1]);
assign RAM1_SEL  = (RAM1_ADRS[15:12]  == CPU_PC[15:12]);


assign INTRNL_ADDRS = ~|CPU_PC[15:12];

// 
// CPU RD data bus input mux
//

always @(CPU_PC or PIOA_D or PIOB_D or PIOWK_D or CNTRA_D or CNTRB_D or CNTRC_D or SCIA_D or EXPWN_D or RAM1_D) begin
	casex (CPU_PC)
		PIOA_ADRS  	: RD_INTRNL = PIOA_D;