expwin.v

q6805.zip

																						
	module ExpWin ( BlockSel,
			   		RegSel,
					INTRNL_ADDRS,
			   		CPUWR,
					CPURD,
			   		CPUClock, 
					EClockStretch,
					NotWClock,
					AddrsIn,
					AddrsOutQ,
					CSP0_n,
					CSP1_n,
					CSD0_n,
					CSD1_n,
					CS3_n,
					CS2_n,
					CS1_n,
					CS0_n,
			   		DIn,
					WaitReqQ,
			   		DOut,
			   		Reset,
			   		Ready);

	input 			BlockSel,
					INTRNL_ADDRS,
					CPUWR,
					CPURD,
					CPUClock,
					EClockStretch,
					NotWClock,
					Reset,
					Ready;

	input [1:0]		RegSel;
	input [7:0] 	DIn;
	input [15:0]	AddrsIn;

	output [7:0] 	DOut;

	output [21:0]   AddrsOutQ;

	output			CSP0_n,
					CSP1_n,
					CSD0_n,
					CSD1_n,
					CS3_n,
					CS2_n,
					CS1_n,
					CS0_n,
					WaitReqQ;

	reg	 [7:0] 	    PWax;
	reg	 [7:0] 	    DWax;
	reg	 [7:0] 	    CSCNTRL;
	reg	 [7:0] 	    WSTG;
	reg	 [7:0] 	    DOut;
	reg				WaitReqQ;
	reg	[1:0]		WaitCount;
	reg	[1:0]		WaitLength;

 	wire  [21:0]	AddrsOutQ;
	wire [21:14]	AddrsOut;
	wire			BUS_CYCL = CPUWR | CPURD;
	wire	    	CSP0;
	wire		    CSP1;
	wire		    CSD0;
	wire		    CSD1;
	wire		    CS3;
	wire		    CS2;
	wire		    CS1;
	wire		    CS0;
    wire			CSP0_n = !(CSP0 & BUS_CYCL & ~INTRNL_ADDRS); 
	wire			CSP1_n = !(CSP1 & BUS_CYCL & ~INTRNL_ADDRS); 
	wire			CSD0_n = !(CSD0 & BUS_CYCL & ~INTRNL_ADDRS); 
	wire			CSD1_n = !(CSD1 & BUS_CYCL & ~INTRNL_ADDRS); 
	wire			CS3_n  = !(CS3  & BUS_CYCL & ~INTRNL_ADDRS);  
	wire			CS2_n  = !(CS2  & BUS_CYCL & ~INTRNL_ADDRS);  
	wire			CS1_n  = !(CS1  & BUS_CYCL & ~INTRNL_ADDRS);  
	wire			CS0_n  = !(CS0  & BUS_CYCL & ~INTRNL_ADDRS);  
	wire			WindowActive;
	wire			WaitReq;
	wire PWaxSel     = BlockSel & (RegSel[1:0] == 2'b00) & Ready;
	wire DWaxSel     = BlockSel & (RegSel[1:0] == 2'b01) & Ready;
	wire CntrlSel    = BlockSel & (RegSel[1:0] == 2'b10) & Ready;
	wire WSTGSel     = BlockSel & (RegSel[1:0] == 2'b11) & Ready;
	wire NotClock;
	wire [1:0] 		WaitGroup;

		
	assign AddrsOutQ =  {AddrsOut, AddrsIn[13:0]};
	assign NotClock = !CPUClock;
	assign WindowActive = CSP1 | CSD1;
	assign CSP0 = CSCNTRL[7] & !CSP1 & !CSD0 & !CSD1 & !CS3 & !CS2 & !CS1 & !CS0 & ~Reset; 
	assign CSP1 = CSCNTRL[6] & (AddrsIn[15:14] == 2'b10) & ~Reset;
	assign CSD0 = CSCNTRL[5] & !AddrsIn[15] & !CSD1 & !CS3 & !CS2 & !CS1 & !CS0;
	assign CSD1 = CSCNTRL[4] & (AddrsIn[15:14] == 2'b01);
	assign CS3  = CSCNTRL[3] & (AddrsIn[15:7] == 9'b0000_0100_1);
	assign CS2  = CSCNTRL[2] & (AddrsIn[15:7] == 9'b0000_0100_0);
	assign CS1  = CSCNTRL[1] & (AddrsIn[15:7] == 9'b0000_0011_1);
	assign CS0  = CSCNTRL[0] & (AddrsIn[15:7] == 9'b0000_0011_0);
	assign AddrsOut = WindowActive ? (CSP1 ? PWax : DWax) : {6'b1111_11, AddrsIn[15:14]};
	assign WaitGroup[1] =  CSP0 | CSP1 | CSD0 | CSD1;
	assign WaitGroup[0] =  CSP0 | CSP1 | CS3  | CS2;

	
	always @(posedge CPUClock or posedge Reset) begin
		if (Reset) begin
			PWax    <= 8'hFF;
			DWax    <= 8'h00;
			CSCNTRL <= 8'h80;							//CSP0 is enabled at Reset
			WSTG	<= 8'hFF;							//everybody gets 3 wait states at powerup
		end
		else begin
			if (PWaxSel & CPUWR) begin
			   	PWax[7:0] <= DIn[7:0];							 
			end
			if (DWaxSel & CPUWR) begin							 
			   	DWax[7:0] <= DIn[7:0];
			end													 
			if (CntrlSel & CPUWR) begin
			   	CSCNTRL[7:0] <= DIn[7:0];						 
			end
			if (WSTGSel & CPUWR) begin
			   	WSTG[7:0] <= DIn[7:0];
			end

		end
	end

	always @(posedge NotWClock or posedge Reset) begin
		if (Reset) begin
			WaitReqQ <= 1'b1;
			WaitCount <= 2'b0;
		end
		else if (~INTRNL_ADDRS) begin
			if (!(WaitCount == WaitLength)) begin
				WaitReqQ <= 1'b0;
				WaitCount <= WaitCount + 1;
			end
			else begin
				WaitReqQ <= 1'b1;
				WaitCount <= 2'b0;
			end
		end
	end

    
    always @(RegSel or PWax or DWax or CSCNTRL or WSTG) begin
    	case (RegSel)   
			2'b00 : DOut = PWax;
			2'b01 : DOut = DWax;
			2'b10 : DOut = CSCNTRL;
			2'b11 : DOut = WSTG;
		endcase
	end

	always @(WSTG or WaitGroup) begin
		
		casex (WaitGroup)
			2'b00 : WaitLength[1:0] = WSTG[1:0];
			2'b01 : WaitLength[1:0] = WSTG[3:2];
			2'b10 : WaitLength[1:0] = WSTG[5:4];
			2'b11 : WaitLength[1:0] = WSTG[7:6];
			default : WaitLength[1:0] = 2'bxx;
		endcase
	end

			

endmodule	//ExpWin