pio8.v

q6805.zip

																						
	module PIO8 (  BlockSel,
			   		RegSel,
			   		CPUWR,
			   		CPUClock,
			   		IOPort,
			   		DIn,
			   		DOut,
			   		Reset,
			   		Ready);

	input 			BlockSel,
					RegSel,
					CPUWR,
					CPUClock,
					Reset,
					Ready;

	inout [7:0] 	IOPort;
	input [7:0] 	DIn;

	output [7:0] 	DOut;

	reg [7:0] DDR;
	reg [7:0] DReg;
	reg [7:0] DOut;


	wire DRegSel  = BlockSel & (RegSel == 1'b0) & Ready;
	wire DDRSel   = BlockSel & (RegSel == 1'b1) & Ready;

	wire [7:0] 	IOPort;									   // these are the actual pins
	wire [7:0]  DRegIn;

			   
	assign IOPort[7] = DDR[7] ? DReg[7] : 1'bz;
	assign IOPort[6] = DDR[6] ? DReg[6] : 1'bz;
	assign IOPort[5] = DDR[5] ? DReg[5] : 1'bz;
	assign IOPort[4] = DDR[4] ? DReg[4] : 1'bz;
	assign IOPort[3] = DDR[3] ? DReg[3] : 1'bz;
	assign IOPort[2] = DDR[2] ? DReg[2] : 1'bz;
	assign IOPort[1] = DDR[1] ? DReg[1] : 1'bz;
	assign IOPort[0] = DDR[0] ? DReg[0] : 1'bz;

	assign DRegIn = IOPort;
	
	always @(posedge CPUClock or posedge Reset) begin
		if (Reset)
			DDR[7:0] <= 8'h00;
		else begin
			if (DDRSel & CPUWR) begin
			   	DDR[7:0] <= DIn[7:0];
			end
		end
	end

	always @(posedge CPUClock or posedge Reset) begin
		if (Reset)
			DReg[7:0] <= 8'h00;
		else begin
			if (DRegSel & CPUWR) begin
			   	DReg[7:0] <= DIn[7:0];
			end
		end
	end

    
    always @(RegSel or DDR or DRegIn) begin
    	case (RegSel)   
			1'b0 : DOut = DRegIn;
			1'b1 : DOut = DDR;
		endcase
	end

endmodule	//PIO8