q6805_cpu.v

q6805.zip

`timescale 1ns/1ns  

module Q6805_CPU( CLK_2Xi,
				  CLK_2Xo,
				  CPU_CLK,
 				  WClockp,
				  EClock,
				  EClock_n,
				  EClockStretch,
			  	  CPU_PC,
				  RD_D,
				  WR_D,
			      WR_n,
			      WRDELq,
			      WRQ1,	
			      RD_n,
				  RDQ1,
			      OPCOD_n,
			      FETCH_n,
			      IACK_n,
			      DISC_n,
				  INT,
				  ACC,
				  XREG,
				  CCR,
				  PROD,
				  VECTOR,
				  STACK_BASE,
				  STK_PTR,
			      WAITNG_n,
			      STOPD_n,
			      RESET_n,
				  RESET,
		          READY,
			      CPU_RDY,
				  MULE,
			      TCK,
			      TDI,
			      TDO,
			      TMS,
			      TRST_n,
				  EVNT0_n,
				  EVNT1_n );

input CLK_2Xi;
inout CLK_2Xo;
output WClockp;
output CPU_CLK;
output EClock;
inout EClock_n;
output EClockStretch;
output [15:0] CPU_PC;
input  [7:0] RD_D;
output [7:0] WR_D;
output WR_n;
output WRDELq;
output WRQ1;
output RD_n;
output RDQ1;
output OPCOD_n;
output FETCH_n;
output IACK_n;
output DISC_n;
input  [5:0] INT;
output [7:0] ACC;
output [15:0] XREG;
output [7:0] CCR;
input  [15:0] PROD;
input  [15:5] VECTOR;
input  [15:6] STACK_BASE;
output [15:0] STK_PTR;
output WAITNG_n;
output STOPD_n;
input  RESET_n;
output RESET;
input  READY;
output CPU_RDY;
input  MULE;
input  TCK;
input  TDI;
input  TMS;
input  TRST_n;
output TDO;
inout  EVNT0_n;
output EVNT1_n;

reg Clock;
reg EClockStretch;
reg ResetSync;
reg WClock;




wire [7:0] RD_D;
wire [7:0] WR_D;
wire EClock;


wire WRq;
wire WRDELq;
wire CPU_RESET;
wire [15:0] CPU_PC;
wire [7:0] MON_INST;
wire [7:0] MON_WR_DAT;
wire [15:0] MON_ADR;
wire [15:0] STK_PTR;
wire CLK_LM;
wire CPU_RDY;
wire MFUNC;
wire MON_CYC_CMPLT;
wire MCMPLT_n;
wire MSR_CMPLT;
wire MON_IN_SRVC;
wire MON_IN_SRVC_n;
wire WAITNG;
wire MFUNC_REQ;
wire STOPD;
wire BRK_CMPLT;
wire BRK_CMPLT_n;
wire BRK_IN_SRVC;
wire BRK_IN_SRVC_n;
wire UPDAT_STAT;
wire BRK_PND;
wire BRK_REQ;
wire BRK_REQ_n;
wire OPCODq;
wire DSCNTYq;
wire IACKq;
wire RD;
wire FETCHq;
wire BREAK;
wire CNTR_EVNT;
wire EVNT0_IN;
wire XCLK_L;		
wire READY;	
wire RESET;
wire CPU_CLK;
wire TCK;	
wire TMS;	
wire TDO_OE;
wire TDO;
wire J_TDO;	
wire TDI;	
wire J_XTRST;
wire OSCi;
wire OSCi_n;
wire OSCobi_n;
wire OSCobi;
wire EVNT1_n;
wire EVNT0_n;
wire [7:0] ACC;
wire [15:0] XREG;
wire [7:0] CCR;
wire [15:0] PROD;
wire [15:5] VECTOR;
wire [15:6] STACK_BASE;
wire FETCH1;
wire IACK1;
wire WRQ1;
wire MULE = 1'b0;
wire WR_n;
wire RDQ1;
wire RD_CLK;




assign WR_n = !WRq;

assign CLK_LM = WClock;
assign WAITNG_n = !WAITNG;
assign OPCOD_n = !OPCODq;
assign STOPD_n = !STOPD;
assign IACK_n = !IACKq;
assign RD_n = !RD;
assign FETCH_n = !FETCHq;
assign EVNT1_n = CNTR_EVNT ? 1'b0 : 1'bz;
assign EVNT0_IN = !EVNT0_n;
assign EVNT0_n = BREAK ? 1'b0 : 1'bz;
assign XCLK_L = !CPU_CLK;		 
assign TDO = TDO_OE ? J_TDO : 1'bz;	
assign DISC_n = !DSCNTYq;
assign BRK_REQ_n = !BRK_REQ;
assign BRK_IN_SRVC_n = !BRK_IN_SRVC;
assign MCMPLT_n = !MON_CYC_CMPLT;
assign MON_IN_SRVC_n = !MON_IN_SRVC;
assign BRK_CMPLT_n = !BRK_CMPLT;

assign OSCi_n = !(CLK_2Xi & !STOPD);
assign OSCi   =   CLK_2Xi & !STOPD;
assign CLK_2Xo = OSCi_n;				
assign OSCobi_n = CLK_2Xo;
assign OSCobi = !CLK_2Xo;
assign EClock = !Clock;
assign EClock_n = Clock;
assign WClockp = WClock;



//gclkbuff_25um cpu_gclk(.A(Clock), .Z(CPU_CLK));


assign CPU_CLK = Clock;

initial begin					 // this is just to put the register in a known state for simulation purposes
	force WClock = 1'b0;
	force Clock = 1'b0;
	force EClockStretch = 1'b1;
	force ResetSync = 1'b1;

	#10
	release WClock;
	release Clock;
	release EClockStretch;
	release ResetSync;
end


core core ( 
		 .ACC({ACC[7:0]}),
		 .BRK_CMPLT(BRK_CMPLT),
 		 .BRK_IN_SRVC(BRK_IN_SRVC), 
 		 .BRK_PND(BRK_PND),
		 .CCR({CCR[7:0]}),
         .CLK(CPU_CLK), 
         .CLK_LM(CLK_LM), 
         .CPU_RDY(CPU_RDY),
         .DB(RD_D), 
         .DISCNTY_G(DSCNTYq), 
         .DOUT({ WR_D[7:0] }),
         .FETCH(FETCHq), 
         .FETCH1(FETCH1), 
         .FRST_WRD(OPCODq),
         .IACK(IACKq), 
         .IACK1(IACK1), 
         .INT({ INT[5:0] }), 
         .MFUNC(MFUNC),
         .MFUNC_REQ(MFUNC_REQ), 
         .MON_ADRS({ MON_ADR[15:0] }),
         .MON_CYC_CMPLT(MON_CYC_CMPLT), 
         .MON_IN_SRVC(MON_IN_SRVC),
         .MON_INST({ MON_INST[7:0] }), 
         .MON_WR_DAT({ MON_WR_DAT[7:0] }),
		 .MULE(MULE),
         .MSR_CMPLT(MSR_CMPLT), 
         .NMI(BRK_REQ), 
         .PC({ CPU_PC[15:0] }), 
		 .PROD({PROD[15:0]}),
         .RD(RD),
         .RDQ1(RDQ1), 
         .READY(READY), 
         .RESET(RESET),
         .STACK({ STK_PTR[15:0] }), 
		 .STACK_BASE({STACK_BASE[15:6]}),
         .STOPD(STOPD), 
         .UPDAT_STAT(UPDAT_STAT),
		 .VECTOR({VECTOR[15:5]}),
         .WAITNG(WAITNG), 
         .WR(WRq), 
         .WR_DEL(WRDELq), 
         .WRQ1(WRQ1),
         .XCLK_L(XCLK_L),
         .XREG({XREG[15:0]}));


debug debug ( 
		 .BREAK(BREAK), 
	     .BRK_CMPLT(BRK_CMPLT), 
         .BRK_IN_SRVC(BRK_IN_SRVC),
         .BRK_PND(BRK_PND), 
         .BRK_REQ(BRK_REQ), 
         .CLR_MFUNC(UPDAT_STAT),
         .CNTR_EVNT(CNTR_EVNT), 
         .CPU_CLK(CPU_CLK),
         .CPU_DISC(DSCNTYq), 
         .CPU_FRST_WRD(OPCODq), 
         .CPU_FTCH(FETCH1), 
         .CPU_PC({ CPU_PC[15:0] }),
         .CPU_RD(RDQ1), 
         .CPU_RDY(CPU_RDY), 
         .CPU_RESET(RESET),
         .CPU_STOP(STOPD), 
         .CPU_WAIT(WAITNG), 
         .CPU_WR(WRQ1),
         .DB(RD_D), 
         .EVNT0_IN(EVNT0_IN),
         .EXT_RESET_IN(ResetSync), 
		 .IACKq(IACKq),
         .MFUNC_CMPLT(MON_CYC_CMPLT),
         .MFUNC_REQ(MFUNC_REQ), 
         .MON_ADR({ MON_ADR[15:0] }),
         .MON_DAT({ MON_WR_DAT[7:0] }), 
         .MON_EXC(MFUNC),
         .MON_IN_SRVC(MON_IN_SRVC), 
         .MON_OPCD({ MON_INST[7:0] }),
         .MSR_CMPLT(MSR_CMPLT), 
         .STK_PTR({ STK_PTR[7:0] }), 
         .TCK(TCK),
         .TDI(TDI), 
         .TDO(J_TDO), 
         .TDO_OE(TDO_OE), 
         .TMS(TMS),
         .XCLK_L(XCLK_L), 
         .XTCK(!TCK), 
         .XTRST(TRST_n) );


always @(posedge OSCobi_n ) begin
		Clock <= !Clock;
		if (!Clock & CPU_RDY) EClockStretch <= 1'b0;
		else if (Clock) EClockStretch <= 1'b1;
end

always @(posedge CPU_CLK) begin
	 ResetSync <= !RESET_n;
end


always @(posedge OSCobi ) begin
		WClock <= !Clock;
end



endmodule // Q6805_CPU