readme.txt

q6805.zip

-------------- Q6805 CPU Netlist Library README File ------------------
Release Version 1.00
November 5, 2003
For Technical Assistance, Contact:

QuickCores
811 E. Plano Parkway, Suite 115
Plano, TX  75074
[phone]
email: [e-mail]
www.quickcores.com

Included in this .zip file are the following Verilog files:

Q6805_TOP.v	// example top-level design
Q6805_TOP.tf	// example test fixture provides external memory, reset and clock source
SINE_MOD.v	// compiled C exercise program converted to .v format for loading into test fixture
Q6805_CPU.v	// core.v and debug.v netlists are instantiated and combined here
core.v		// Q6805 CPU netlist
debug.v		// JTAG debug module with TAP, event counter, PC discontinuity trace, real-time monitor H/W
SCI8DR.v	// asynchronous serial port Verilog RTL
CNTR8.v		// 8-bit timer/counter in Verilog RTL
PIO8.v		// 8-bit parallel I/O port with programmable data direction in Verilog RTL
PIO8WK.v	// 8-bit parallel I/O port with keyboard wake up feature in Verilog RTL
EXPWIN.v	// 8-megabyte windowed extended address circuit with programmable wait-state generator in Verilog RTL
DAC7512.v	// 12-bit DAC serial serial interface in Verilog RTL

The following C source and lising files are also included:

SINE_MOD.c	// example C source file for exercising above example design
SINE_MOD.LST	// listing file created from above C source code