core.v

q6805.zip

mux7_bit I_17 ( .A(A[7]), .B(B[7]), .C(C[7]), .D(D[7]), .DOUT(Y[7]), .E(E[7]),
             .F(F[7]), .G(G[7]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );

endmodule // mux7x8

`endif


`ifdef half_os
`else
`define half_os
module half_os( CLK , CLR, D, E, XCLK, Q );
input CLK, CLR, D, E;
output Q;
input XCLK;


reg Q;
reg CLR_Q;

wire Q_CLR = CLR | CLR_Q;
wire Q_n = ~Q;

always @(posedge XCLK or posedge Q_CLR) begin
	if (Q_CLR) begin
		Q <= 1'b0;
	end
	else begin
		Q <= D;
	end
end

always @(posedge CLK or posedge Q_n) begin
	if (Q_n) begin
		CLR_Q <= 1'b0;
	end
	else begin
		if (E) CLR_Q <= Q;
	end
end

endmodule // half_os

`endif

`ifdef mux16
`else
`define mux16
module mux16( A , B, S, Y );
 input [15:0] A;
 input [15:0] B;
input S;
 output [15:0] Y;

wire [15:0] Y;

assign Y = S ? B : A;

endmodule // mux16

`endif

`ifdef csadd16c
`else
`define csadd16c
module csadd16c( A , B, CI, Q );
 input [15:0] A;
 input [15:0] B;
input CI;
 output [15:0] Q;

wire [15:0] Q;

assign Q = A + B + CI;

endmodule // csadd16c

`endif

`ifdef dat_ptr
`else
`define dat_ptr
module dat_ptr( CLK , CLR_DP_HI, CLR_DP_L, EN_DP_HI, NEG_ADND, NEG_ONE, OPRND,
                READY, DP );
input CLK, CLR_DP_HI, CLR_DP_L;
 output [15:0] DP;
input EN_DP_HI, NEG_ADND, NEG_ONE;
 input [7:0] OPRND;
input READY;

reg [15:8] DPX;
wire N_1;
wire N_2;
wire N_3;
wire N_4;
wire N_5;
wire N_6;
wire N_7;
wire N_8;
wire N_9;
wire N_10;
wire N_11;
wire NEG;
wire CLR;
wire [15:0] DP;

supply0 GND;
supply1 VCC;

assign N_8 = CLR_DP_HI ? 1'b0 : DPX[15];
assign N_7 = CLR_DP_HI ? 1'b0 : DPX[14];
assign N_6 = CLR_DP_HI ? 1'b0 : DPX[13];
assign N_5 = CLR_DP_HI ? 1'b0 : DPX[12];
assign N_4 = CLR_DP_HI ? 1'b0 : DPX[11];
assign N_3 = CLR_DP_HI ? 1'b0 : DPX[10];
assign N_2 = CLR_DP_HI ? 1'b0 : DPX[9];
assign N_1 = CLR_DP_HI ? 1'b0 : DPX[8];

always @(posedge CLK) begin
	if (N_11) DPX[15:8] <= OPRND[7:0];
end

assign DP[15] = N_8 | N_9 | N_10;
assign DP[14] = N_7 | N_9 | N_10;
assign DP[13] = N_6 | N_9 | N_10;
assign DP[12] = N_5 | N_9 | N_10;
assign DP[11] = N_4 | N_9 | N_10;
assign DP[10] = N_3 | N_9 | N_10;
assign DP[9] = N_2 | N_9 | N_10;
assign DP[8] = N_1 | N_9 | N_10;
 
assign N_9 = NEG_ONE;
assign NEG = NEG_ONE;
assign CLR = CLR_DP_L;

assign DP[7:0] = NEG ? 8'hFF : (CLR ? 8'b0 : OPRND[7:0]);
assign N_10 = NEG_ADND & OPRND[7];
assign N_11 = READY & EN_DP_HI;

endmodule // dat_ptr

`endif

`ifdef stack
`else
`define stack
module stack( CLK , EN_STK_PTR, POP_PUSH, READY, RESET, RSP, STACK_BASE, XCLK_L,
              SPQ );
input CLK, EN_STK_PTR, POP_PUSH, READY, RESET, RSP;
 output [15:0] SPQ;
 input [15:6] STACK_BASE;
input XCLK_L;

reg [5:0] Q;

wire [15:0] SPQ;

assign SPQ = {STACK_BASE, Q};


always @(posedge CLK or posedge RESET) begin
	if (RESET) begin
		Q <= 6'b0;
	end
	else begin
		if ( READY & EN_STK_PTR) begin
			Q <= Q + (POP_PUSH ? 6'b111111: 6'b000001);
		end
		else if (READY & RSP) Q <= 6'b0;
	end
end

endmodule // stack

`endif



`ifdef mux16x4
`else
`define mux16x4
module mux16x4( A , B, C, D, S0, S1, Y );
 input [15:0] A;
 input [15:0] B;
 input [15:0] C;
 input [15:0] D;
input S0, S1;
 output [15:0] Y;

wire [15:0] Y;

assign Y= S1 ? (S0 ? D : C) : (S0 ? B : A);


endmodule // mux16x4

`endif


`ifdef vect
`else
`define vect
module vect( CLK , EN_IACK, FRST_WRD, IF, IRQ, MFUNC, MRTI, NMI, READY, RESET,
             SBRK, SEQ_CMPLT, SWI, VECTOR, XCLK_L, BRK_IN_SRVC, BRK_PND,
             INT_SEQ, IRQ_DET, RESET_SEQ, VECT );
output BRK_IN_SRVC, BRK_PND;
input CLK, EN_IACK, FRST_WRD, IF;
output INT_SEQ;
 input [5:0] IRQ;
output IRQ_DET;
input MFUNC, MRTI, NMI, READY, RESET;
output RESET_SEQ;
input SBRK, SEQ_CMPLT, SWI;
 output [15:0] VECT;
 input [15:5] VECTOR;
input XCLK_L;

reg [4:1] VECT_R;
reg RESET_SEQ;
reg BRK_IN_SRVC;
reg INT_SEQ;

wire [4:1] VD;
wire [6:0] INT_PND;
wire INT_DET;
wire IRQ_DET;
wire [15:0] VECT;

supply0 GND;


assign VD[4] = ~(~RESET_SEQ & BRK_PND);
assign IRQ_DET = (|IRQ[5:0]) | NMI;
assign VECT[15:0] = {VECTOR[15:5], VECT_R[4:1], 1'b0}; 


always @(posedge CLK) begin
	VECT_R[4:1]	<= VD[4:1];
end

always @(posedge CLK or posedge RESET) begin
	if (RESET) begin
		RESET_SEQ <= 1'b1;
	end
	else begin
		if (READY & EN_IACK & RESET_SEQ) RESET_SEQ <= 1'b0;
	end
end

always @(posedge CLK or posedge RESET) begin
	if (RESET) begin
		BRK_IN_SRVC <= 1'b0;
		INT_SEQ <= 1'b0;
	end
	else begin
		if (READY) begin
			BRK_IN_SRVC <= (SEQ_CMPLT & MRTI) ? 1'b0 : ((BRK_PND & EN_IACK) | BRK_IN_SRVC);
			INT_SEQ      <= EN_IACK ? 1'b0 : (((SBRK | SWI | FRST_WRD) & INT_DET & ~RESET_SEQ & ~MFUNC) | INT_SEQ);
		end
	end
end
		 


irq_reg I_64 ( .BRK_PND(BRK_PND), .CPU_CLK(CLK), .EN_IACK(EN_IACK), .IF(IF),
            .INT_SEQ(INT_SEQ), .IRQ({ IRQ[5:0] }),
            .IRQ_MSK({ GND,GND,GND,GND,GND,GND }),
            .IRQ_PEND({ INT_PND[6:0] }), .NMI(NMI), .READY(READY),
            .RESET(RESET), .SBRK(SBRK), .SWI(SWI), .VECT({ VECT[3:1] }),
            .XCLK_L(XCLK_L) );

pri_enc I_26 ( .A0(VD[1]), .A1(VD[2]), .A2(VD[3]), .DET(INT_DET), .I0(INT_PND[0]),
            .I1(INT_PND[1]), .I2(INT_PND[2]), .I3(INT_PND[3]),
            .I4(INT_PND[4]), .I5(INT_PND[5]), .I6(INT_PND[6]), .I7(RESET_SEQ | BRK_PND) );

endmodule // vect

`endif


`ifdef othr_seq
`else
`define othr_seq
module othr_seq( ADC , ADD, AND, BIT, BRK_PND, CLC, CLI, CMP, CPU_CLK, CPX, DIRB,
                 EOR, EXT, IMM, INT_SEQ, INT_STAT, INVALID, IX1E, IX2D, IXF,
                 JMP, JSR, LDA, LDX, LOI, MFUNC, MRD, MRET, MRTI, MUL, MULE,
                 MWR, NOP, ORA, RESET, RSP, RST_SEQ, RTI, RTS, SBC, SBRK, SEC,
                 SEI, STA, STATE, STOP, STX, SUB, SWI, TAX, TXA, WAIT, WORM,
                 ACC_SRC_SEL0, ACC_SRC_SEL1, ADD_1_PC, CF_SEL0, CF_SEL1,
                 CF_SEL2, CF_SEL3, CF_SEL4, CLR_DP_H, CLR_DP_L, DIS_FTCH,
                 DIS_PC, DIS_PC_TRK, DIS_RD, DIS_STATE, DISCNTY, EN_ACC,
                 EN_CF, EN_DP_H, EN_HC, EN_IACK, EN_IF, EN_NF, EN_STK_PTR,
                 EN_WR, EN_XREG, EN_ZF, IF_SEL0, IF_SEL1, INT_STB7, LD_ACC,
                 LD_PC, LD_PC_TRK, LD_XREG, NEG_ADND, NEG_ONE, NF_SEL0,
                 OUT_MON, OUT_PCH, OUT_PCL, OUT_XREG, PC_XREG, POP, RESTOR,
                 RTI_STB3, SEL_BOOL, SEL_FF_00, SEL_MON_ADRS, SEL_STK_PTR,
                 SEL_VECT, SEL_XREG_A, SEQ_CMPLT, SUB_A, X_SRC_SEL0,
                 X_SRC_SEL1, ZERO, ZF_SEL0 );
output ACC_SRC_SEL0, ACC_SRC_SEL1;
input ADC, ADD;
output ADD_1_PC;
input AND, BIT, BRK_PND;
output CF_SEL0, CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4;
input CLC, CLI;
output CLR_DP_H, CLR_DP_L;
input CMP, CPU_CLK, CPX, DIRB;
output DIS_FTCH, DIS_PC, DIS_PC_TRK, DIS_RD, DIS_STATE, DISCNTY, EN_ACC,
EN_CF, EN_DP_H, EN_HC, EN_IACK, EN_IF, EN_NF, EN_STK_PTR, EN_WR,
EN_XREG, EN_ZF;
input EOR, EXT;
output IF_SEL0, IF_SEL1;
input IMM, INT_SEQ;
 input [9:0] INT_STAT;
output INT_STB7;
input INVALID, IX1E, IX2D, IXF, JMP, JSR;
output LD_ACC, LD_PC, LD_PC_TRK, LD_XREG;
input LDA, LDX, LOI, MFUNC, MRD, MRET, MRTI, MUL, MULE, MWR;
output NEG_ADND, NEG_ONE, NF_SEL0;
input NOP, ORA;
output OUT_MON, OUT_PCH, OUT_PCL, OUT_XREG, PC_XREG, POP;
input RESET;
output RESTOR;
input RSP, RST_SEQ, RTI;
output RTI_STB3;
input RTS, SBC, SBRK, SEC, SEI;
output SEL_BOOL, SEL_FF_00, SEL_MON_ADRS, SEL_STK_PTR, SEL_VECT, SEL_XREG_A,
SEQ_CMPLT;
input STA;
 input [9:1] STATE;
input STOP, STX, SUB;
output SUB_A;
input SWI, TAX, TXA, WAIT, WORM;
output X_SRC_SEL0, X_SRC_SEL1, ZERO, ZF_SEL0;
wire [9:1] STB;
wire N_3;
wire ACC_SRC_SEL1_b;
wire X_SRC_SEL1_b;
wire JMP_ST12;
wire N_1;
wire N_2;
wire INT_STB1;
wire INT_ST16;
wire INT_STB8;
wire INT_STB9;
wire JSR_STB45;
wire EN_LD_ACC_c;
wire EN_LD_XREG_c;
wire RST_LD_PC;
wire CF_SEL432_b;
wire CF_SEL4321_a;
wire EN_ZF_NF_a;
wire ZF_NF_SEL0_a;
wire SEL_MON_ADRS_d;
wire SEL_MON_ADRS_e;
wire PC_XREG_c;
wire ZERO_c;
wire ADD_1_PC_d;
wire NEG_ONE_c;
wire ADD_1_PC_c;
wire NEG_ONE_d;
wire DIS_PC_TRK_d;
wire CLR_DP_L_a;
wire LD_PC_TRK_d;
wire LD_PC_TRK_e;
wire LD_PC_TRK_f;
wire SEL_VECT_g;
wire LD_XREG_a;
wire LD_ACC_a;
wire LD_XREG_b;
wire X_SRC_SEL0_b;
wire LD_ACC_b;
wire ACC_SRC_SEL0_b;
wire EN_IF_b;
wire IF_SEL0_b;
wire EN_STK_PTR_c;
wire SEL_STK_PTR_c;
wire DIS_PC_c;
wire LD_PC_TRK_c;
wire DISCNTY_c;
wire DIS_RD_c;
wire DIS_RD_d;
wire OUT_PCH_d;
wire OUT_PCL_d;
wire PC_XREG_d;
wire DIS_PC_d;