core.v

q6805.zip

input FETCH, FRST_WRD;
output IMM, INC, INH4, INH5, INH8, INH9;
 input [7:0] INSTR;
input INT_SEQ;
 output [9:0] INT_STAT;
output INVALID, IX16, IX1E, IX2D, IX7, IXF, JMP, JSR, LDA, LDX, LOI, LSL, LSR,
MFUNC;
input MFUNC_REQ;
output MON_CYC_CMPLT, MON_IN_SRVC;
 input [7:0] MON_INST;
output MRD, MRET, MRTI, MSR_CMPLT, MUL, MWR, NEG, NOP, ONE_CYC;
 output [7:0] OPCOD;
output ORA;
input READY;
output REL;
input RESET;
output ROL, ROR, RSP;
input RST_SEQ;
output RTI, RTS, SBC, SBRK, SEC, SEI;
input SEQ_CMPLT;
output STA;
 output [9:1] STATE;
output STOP, STX, SUB, SWI, TAX, TST, TXA;
input UDAT_STAT;
output WAIT, WORM;
wire [15:0] LOW;
wire [7:0] OPCODA;
wire [7:4] OP_89;
wire N_14;
wire N_13;
wire STATE0;
supply0 GND;
supply1 VCC;

reg N_12;

wire N_6;
assign N_14 = STOP | WAIT;
assign N_13 = N_12 & ~RST_SEQ & ~INT_SEQ & ~STATE0;
assign DECODE = N_12 & STATE[1] & ~INT_SEQ & ~RST_SEQ;
assign ONE_CYC = INH9 | INH5 | INH4 | N_14;
assign N_6 = READY & FRST_WRD;
always @(posedge CLK or posedge RESET) begin
	if (RESET) begin
		N_12 <= 1'b0;
	end
	else begin
		if (N_6) N_12 <= 1'b1;
	end
end


inst_que I_13 ( .BRK_CMPLT(BRK_CMPLT), .BRK_IN_SRVC(BRK_IN_SRVC), .CLK(CLK),
             .CPU_RESET(RESET), .DB_MXD({ DB_MXD[7:0] }), .FETCH(FETCH),
             .FRST_WRD(FRST_WRD), .INSTR({ INSTR[7:0] }), .JSR(JSR),
             .MFUNC(MFUNC), .MFUNC_REQ(MFUNC_REQ),
             .MON_CYC_CMPLT(MON_CYC_CMPLT), .MON_IN_SRVC(MON_IN_SRVC),
             .MON_INST({ MON_INST[7:0] }), .MRET(MRET), .MRTI(MRTI),
             .MSR_CMPLT(MSR_CMPLT), .OP_89({ OP_89[7:4] }),
             .OPCOD({ OPCOD[7:0] }), .OPCODA({ OPCODA[7:0] }), .READY(READY),
             .SEQ_CMPLT(SEQ_CMPLT), .UPDAT_STAT(UDAT_STAT) );
stat_dec I_18 ( .CLK(CLK), .DIS_STATE(DIS_STATE), .INT_SEQ(INT_SEQ),
             .INT_STAT({ INT_STAT[9:0] }), .READY(READY), .RESET(RESET),
             .RST_SEQ(RST_SEQ), .SEQ_CMPLT(SEQ_CMPLT), .STAT0(STATE0),
             .STATE({ STATE[9:1] }) );
dcd_othr I_5 ( .CLC(CLC), .CLI(CLI), .DECOD(N_13), .INVALID(INVALID), .LOI(LOI),
            .LOW({ LOW[15:0] }), .MRD(MRD), .MRET(MRET), .MRTI(MRTI),
            .MWR(MWR), .NOP(NOP), .OP_89({ OP_89[7:4] }), .RSP(RSP), .RTI(RTI),
            .RTS(RTS), .SBRK(SBRK), .SEC(SEC), .SEI(SEI), .STOP(STOP),
            .SWI(SWI), .TAX(TAX), .TXA(TXA), .WAIT(WAIT), .WORM(WORM) );
op_decd I_6 ( .BSC(BSC), .BTB(BTB), .DECD(N_13), .DIR3(DIR3), .DIRB(DIRB),
           .EXT(EXT), .IMM(IMM), .INH4(INH4), .INH5(INH5), .INH8(INH8),
           .INH9(INH9), .IX16(IX16), .IX1E(IX1E), .IX2D(IX2D), .IX7(IX7),
           .IXF(IXF), .LOW({ LOW[15:0] }), .Q({ OPCODA[7:0] }), .REL(REL) );
decd_low I_7 ( .ASR(ASR), .BSC(BSC), .BTB(BTB), .CLR(CLR), .COM(COM),
            .D7(OPCOD[7]), .DEC(DEC), .DECOD(N_13), .INC(INC), .INH4(INH4),
            .LOW({ LOW[15:0] }), .LSL(LSL), .LSR(LSR), .MUL(MUL), .NEG(NEG),
            .REL(REL), .ROL(ROL), .ROR(ROR), .TST(TST) );
decd_upr I_8 ( .ADC(ADC), .ADD(ADD), .AND(AND), .BIT(BIT), .CMP(CMP), .CPX(CPX),
            .D7(OPCOD[7]), .DECOD(N_13), .EOR(EOR), .IMM(IMM), .INH8(INH8),
            .INH9(INH9), .JMP(JMP), .JSR(JSR), .LDA(LDA), .LDX(LDX),
            .LOW({ LOW[15:0] }), .ORA(ORA), .SBC(SBC), .STA(STA), .STX(STX),
            .SUB(SUB) );

endmodule // decode

`endif

`ifdef alu
`else
`define alu
module alu( ACCUM , ADD, ALU_OP_0, ALU_OP_1, AND, COMPL_A, CY_FLG, DB, MREG,
            SEL_BOOL, SEL_FF_00, SEL_MEM_A, SEL_XREG_A, SUB, SUBC, XOR, XREG,
            ALU, COUT_ADDR, HC );
 input [7:0] ACCUM;
input ADD;
 output [7:0] ALU;
input ALU_OP_0, ALU_OP_1, AND, COMPL_A;
output COUT_ADDR;
input CY_FLG;
 input [7:0] DB;
output HC;
 input [7:0] MREG;
input SEL_BOOL, SEL_FF_00, SEL_MEM_A, SEL_XREG_A, SUB, SUBC, XOR;
 input [7:0] XREG;
wire [7:0] FF_01_00;
wire [7:0] TERM_B;
wire [7:0] A_X;
wire [7:0] TERM_A;
wire [7:0] BOOL;
wire [7:0] SUM;

logical I_1 ( .A({ TERM_A[7:0] }), .AND(AND), .B({ TERM_B[7:0] }),
           .Q({ BOOL[7:0] }), .XOR(XOR) );
add_subt I_4 ( .ADD_ADDC(ADD), .CI(CY_FLG), .CO(COUT_ADDR), .COMPL_A(COMPL_A),
            .HC(HC), .SUB(SUB), .SUBC(SUBC), .SUM({ SUM[7:0] }),
            .TERM_A({ TERM_A[7:0] }), .TERM_B({ TERM_B[7:0] }) );
ff_01_00 I_5 ( .ALU_OP_0(ALU_OP_0), .ALU_OP_1(ALU_OP_1),
            .FF_01_00({ FF_01_00[7:0] }) );

assign ALU = SEL_BOOL ? BOOL : SUM;
assign TERM_A = SEL_MEM_A ? MREG : A_X;
assign TERM_B = SEL_FF_00 ? FF_01_00 : DB;
assign A_X = SEL_XREG_A ? XREG : ACCUM;

endmodule // alu

`endif

`ifdef xreg
`else
`define xreg
module xreg( ACCUM , ALU, CLK, CLR, CY_FLG, EN_XREG, LD_XREG, LSL, LSR, MULT, OPRND,
             READY, ROL, ROR, X_SRC_SEL0, X_SRC_SEL1, N, XREG, Z );
 input [7:0] ACCUM;
 input [7:0] ALU;
input CLK, CLR, CY_FLG, EN_XREG, LD_XREG, LSL, LSR;
 input [15:8] MULT;
output N;
 input [7:0] OPRND;
input READY, ROL, ROR, X_SRC_SEL0, X_SRC_SEL1;
 output [15:0] XREG;
output Z;
wire [7:0] Y;
wire [7:0] MXO;
wire N_4;
wire N_1;
wire N_2;
wire [7:0] CLR_BITS;
wire [7:0] SET_BITS;

assign CLR_BITS = ~`SNH & {CLR, CLR, CLR, CLR, CLR, CLR, CLR, CLR}; 
assign SET_BITS =  `SNH & {CLR, CLR, CLR, CLR, CLR, CLR, CLR, CLR}; 


shftunit I_22 ( .CLK(CLK), .CLR({ CLR_BITS[7:0] }), .CY_FLG(CY_FLG),
             .D({ Y[7:0] }), .EN(N_4), .LD(LD_XREG), .LSL(LSL), .LSR(LSR),
             .MXO({ MXO[7:0] }), .PRE({ SET_BITS[7:0] }),
             .Q({ XREG[7:0] }), .ROL(ROL), .ROR(ROR) );

assign N_4 = READY & EN_XREG;
assign Z = N_1 & N_2;
assign N_2 = ~(|MXO[3:0]);
assign N_1 = ~(|MXO[7:4]);
assign Y = X_SRC_SEL1 ? (X_SRC_SEL0 ? OPRND : MULT) : (X_SRC_SEL0 ? ACCUM : ALU);
assign N = MXO[7];
assign XREG[15:8] = 8'b0;

endmodule // xreg

`endif

`ifdef mout_reg
`else
`define mout_reg
module mout_reg( ALU , CLK, CY_FLG, DB, EN_BSC, EN_MREG, LD_MREG, LSL, LSR, OPCOD,
                 READY, ROL, ROR, SEL_DB, BTB_BIT, BTB_TST, MOUT_REG, N, Z );
 input [7:0] ALU;
output BTB_BIT, BTB_TST;
input CLK, CY_FLG;
 input [7:0] DB;
input EN_BSC, EN_MREG, LD_MREG, LSL, LSR;
 output [7:0] MOUT_REG;
output N;
 input [3:0] OPCOD;
input READY, ROL, ROR, SEL_DB;
output Z;

reg BTB_TST;

wire [7:0] PRE;
wire [7:0] CLR;
wire [7:0] Y;
wire [7:0] MXO;
wire N_6;
wire N_7;
wire N_8;
wire N_5;
wire N_1;
wire N_3;
always @(posedge CLK) begin
	if (READY) BTB_TST = N_6;
end
assign N_6 = OPCOD[0] ^ BTB_BIT;
assign Y = SEL_DB ? DB : ALU;

mem_logu I_17 ( .CLK(CLK), .CLR({ CLR[7:0] }), .CY_FLG(CY_FLG), .D({ Y[7:0] }),
             .EN(N_5), .LD(LD_MREG), .LSL(LSL), .LSR(LSR), .MXO({ MXO[7:0] }),
             .PRE({ PRE[7:0] }), .Q({ MOUT_REG[7:0] }), .ROL(ROL), .ROR(ROR) );

bit_twdl I_18 ( .A(OPCOD[1]), .B(OPCOD[2]), .BSC_EN(EN_BSC), .C(OPCOD[3]),
             .CLR({ CLR[7:0] }), .CLR_SET(OPCOD[0]), .PRE({ PRE[7:0] }) );

assign BTB_BIT = OPCOD[3] ? N_8 : N_7;
assign N_8 = OPCOD[2] ? (OPCOD[1] ? DB[7] : DB[6]) : (OPCOD[1] ? DB[5] : DB[4]);
assign N_7 = OPCOD[2] ? (OPCOD[1] ? DB[3] : DB[2]) : (OPCOD[1] ? DB[1] : DB[0]);
assign N = MXO[7];
assign N_5 = READY & EN_MREG;
assign Z = N_1 & N_3;
assign N_3 = ~(|MXO[3:0]);
assign N_1 = ~(|MXO[7:4]);

endmodule // mout_reg

`endif

`ifdef ccr
`else
`define ccr
module ccr( AC_D0 , AC_D7, AC_NF, AC_ZF, ACCUM_HC, ADDR_CF, BTB_BIT, CF_SEL0,
            CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLK, CLR_BT, DB_D0, DB_D1,
            DB_D2, DB_D3, DB_D4, EN_CF, EN_HC, EN_IF, EN_NF, EN_ZF, HC_SEL0,
            IF_SEL0, IF_SEL1, MR_D0, MR_D7, MR_NF, MR_ZF, NF_SEL0, NF_SEL1,
            READY, RESET, RTB, SBRK, XR_D0, XR_D7, XR_NF, XR_ZF, ZF_SEL0,
            ZF_SEL1, CCR );
input AC_D0, AC_D7, AC_NF, AC_ZF, ACCUM_HC, ADDR_CF, BTB_BIT;
 output [7:0] CCR;
input CF_SEL0, CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLK, CLR_BT, DB_D0, DB_D1,
DB_D2, DB_D3, DB_D4, EN_CF, EN_HC, EN_IF, EN_NF, EN_ZF, HC_SEL0,
IF_SEL0, IF_SEL1, MR_D0, MR_D7, MR_NF, MR_ZF, NF_SEL0, NF_SEL1, READY,
RESET, RTB, SBRK, XR_D0, XR_D7, XR_NF, XR_ZF, ZF_SEL0, ZF_SEL1;

reg CCR7;

wire N_22;
wire N_20;
wire N_21;
wire N_15;
wire N_16;
wire N_17;
wire N_18;
wire N_19;
wire N_9;
wire N_10;
wire N_11;
wire N_12;
wire N_13;
wire N_14;
wire N_8;
wire N_3;
wire N_4;
wire N_5;
wire N_6;

wire [7:0] CCR;

assign CCR[7] = CCR7;

supply1 VCC;
supply0 GND;
always @(posedge CLK or posedge RESET) begin
	if (RESET) begin
		CCR7 <= 1'b1;
	end
	else begin
		if (N_21) CCR7 <= N_22;
	end
end
assign N_21 = READY & N_20;
assign N_15 = READY & EN_CF;
assign N_16 = READY & EN_ZF;
assign N_17 = READY & EN_NF;
assign N_18 = READY & EN_IF;
assign N_19 = READY & EN_HC;
assign N_9 = MR_NF & ~CLR_BT;
assign N_10 = XR_NF & ~CLR_BT;
assign N_11 = AC_NF & CLR_BT;
assign N_8 = CF_SEL1 ? (CF_SEL0 ? BTB_BIT : ADDR_CF) : (CF_SEL0 ? 1'b1 : 1'b0);
assign N_20 = SBRK | RTB;
assign N_12 = CLR_BT | MR_ZF;
assign N_13 = CLR_BT | XR_ZF;
assign N_14 = CLR_BT | AC_ZF;
assign N_5 = CF_SEL2 ? MR_D0 : MR_D7;
assign N_6 = CF_SEL2 ? N_8 : DB_D0;
assign N_3 = CF_SEL2 ? AC_D0 : AC_D7;
assign N_4 = CF_SEL2 ? XR_D0 : XR_D7;
assign N_22 = ~SBRK;
assign CCR[6] =  1'b1;
assign CCR[5] = 1'b1;

ccr_bit I_8 ( .A(N_3), .B(N_4), .C(N_5), .CLK(CLK), .CLR(GND), .D(N_6), .EN(N_15),
           .PRE(GND), .Q(CCR[0]), .SEL0(CF_SEL3), .SEL1(CF_SEL4) );
ccr_bit I_7 ( .A(N_14), .B(N_13), .C(N_12), .CLK(CLK), .CLR(GND), .D(DB_D1),
           .EN(N_16), .PRE(GND), .Q(CCR[1]), .SEL0(ZF_SEL0), .SEL1(ZF_SEL1) );
ccr_bit I_6 ( .A(N_11), .B(N_10), .C(N_9), .CLK(CLK), .CLR(GND), .D(DB_D2),
           .EN(N_17), .PRE(GND), .Q(CCR[2]), .SEL0(NF_SEL0), .SEL1(NF_SEL1) );
ccr_bit I_4 ( .A(ACCUM_HC), .B(DB_D4), .C(GND), .CLK(CLK), .CLR(GND), .D(GND),
           .EN(N_19), .PRE(GND), .Q(CCR[4]), .SEL0(HC_SEL0), .SEL1(GND) );
ccr_bit I_5 ( .A(DB_D3), .B(VCC), .C(GND), .CLK(CLK), .CLR(GND), .D(GND), .EN(N_18),
           .PRE(RESET), .Q(CCR[3]), .SEL0(IF_SEL0), .SEL1(IF_SEL1) );

endmodule // ccr

`endif

`ifdef accum
`else
`define accum
module accum( ACUM_SRC_SEL0 , ACUM_SRC_SEL1, ALU, CLK, CLR, CY_FLG, EN_ACCUM, LD_ACCUM, LSL,
              LSR, MULT, OPRND, READY, ROL, ROR, XREG, ACCUM, N, Z );
 output [7:0] ACCUM;
input ACUM_SRC_SEL0, ACUM_SRC_SEL1;
 input [7:0] ALU;
input CLK, CLR, CY_FLG, EN_ACCUM, LD_ACCUM, LSL, LSR;
 input [7:0] MULT;
output N;
 input [7:0] OPRND;
input READY, ROL, ROR;
 input [7:0] XREG;
output Z;
wire [7:0] MXO;
wire [7:0] Y;
wire N_3;
wire N_1;
wire N_2;

wire [7:0] CLR_BITS;
wire [7:0] SET_BITS;

assign CLR_BITS = ~`SNL & {CLR, CLR, CLR, CLR, CLR, CLR, CLR, CLR}; 
assign SET_BITS =  `SNL & {CLR, CLR, CLR, CLR, CLR, CLR, CLR, CLR}; 



shftunit I_10 ( .CLK(CLK), .CLR({CLR_BITS[7:0]}), .CY_FLG(CY_FLG),
             .D({ Y[7:0] }), .EN(N_3), .LD(LD_ACCUM), .LSL(LSL), .LSR(LSR),
             .MXO({ MXO[7:0] }), .PRE({SET_BITS[7:0] }),
             .Q({ ACCUM[7:0] }), .ROL(ROL), .ROR(ROR) );
assign N = MXO[7];
assign N_3 = READY & EN_ACCUM;
assign Z = N_1 & N_2;
assign N_2 = ~(|MXO[3:0]);
assign N_1 = ~(|MXO[7:4]);
assign Y = ACUM_SRC_SEL1 ? (ACUM_SRC_SEL0 ? OPRND : MULT) : (ACUM_SRC_SEL0 ? XREG : ALU);


endmodule // accum

`endif


`ifdef mux7x8
`else
`define mux7x8
module mux7x8( A , B, C, D, E, F, G, S0, S1, S2, S3, Y );
 input [7:0] A;
 input [7:0] B;
 input [7:0] C;
 input [7:0] D;
 input [7:0] E;
 input [7:0] F;
 input [7:0] G;
input S0, S1, S2, S3;
 output [7:0] Y;

mux7_bit I_10 ( .A(A[3]), .B(B[3]), .C(C[3]), .D(D[3]), .DOUT(Y[3]), .E(E[3]),
             .F(F[3]), .G(G[3]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );
mux7_bit I_11 ( .A(A[2]), .B(B[2]), .C(C[2]), .D(D[2]), .DOUT(Y[2]), .E(E[2]),
             .F(F[2]), .G(G[2]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );
mux7_bit I_12 ( .A(A[1]), .B(B[1]), .C(C[1]), .D(D[1]), .DOUT(Y[1]), .E(E[1]),
             .F(F[1]), .G(G[1]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );
mux7_bit I_13 ( .A(A[0]), .B(B[0]), .C(C[0]), .D(D[0]), .DOUT(Y[0]), .E(E[0]),
             .F(F[0]), .G(G[0]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );
mux7_bit I_14 ( .A(A[4]), .B(B[4]), .C(C[4]), .D(D[4]), .DOUT(Y[4]), .E(E[4]),
             .F(F[4]), .G(G[4]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );
mux7_bit I_15 ( .A(A[5]), .B(B[5]), .C(C[5]), .D(D[5]), .DOUT(Y[5]), .E(E[5]),
             .F(F[5]), .G(G[5]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );
mux7_bit I_16 ( .A(A[6]), .B(B[6]), .C(C[6]), .D(D[6]), .DOUT(Y[6]), .E(E[6]),
             .F(F[6]), .G(G[6]), .S0(S0), .S1(S1), .S2(S2), .S3(S3) );